Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/181484
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DC FieldValueLanguage
dc.coverage.spatialInformation and Communication Engineering
dc.date.accessioned2017-11-16T06:53:20Z-
dc.date.available2017-11-16T06:53:20Z-
dc.identifier.urihttp://hdl.handle.net/10603/181484-
dc.description.abstractAbstract available
dc.format.extentxxv, 146p.
dc.languageEnglish US
dc.relation137-145
dc.rightsuniversity
dc.titleDesign of analog input module multiple PID controller and verilog code for ladder diagram using FPGA
dc.title.alternative
dc.creator.researcherG, Dhanabalan
dc.subject.keywordAnalog
dc.subject.keywordDesign
dc.subject.keywordDiagram
dc.subject.keywordModule
dc.subject.keywordVerilog
dc.description.noteData not available
dc.contributor.guideSelvi, S Tamil
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.date.registeredn.d.
dc.date.completed2016
dc.date.awardedn.d.
dc.format.dimensions30cm.
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File24.46 kBAdobe PDFView/Open
02_certificate.pdf633.68 kBAdobe PDFView/Open
03_abstract.pdf101.36 kBAdobe PDFView/Open
04_acknowledgement.pdf4.67 kBAdobe PDFView/Open
05_table of content.pdf192.79 kBAdobe PDFView/Open
06_list of symbol and abbreviations.pdf51.81 kBAdobe PDFView/Open
07_chapter 1.pdf317.89 kBAdobe PDFView/Open
08_chapter 2.pdf1.79 MBAdobe PDFView/Open
09_chapter 3.pdf979.89 kBAdobe PDFView/Open
10_chapter 4.pdf1.54 MBAdobe PDFView/Open
11_chapter 5.pdf1.88 MBAdobe PDFView/Open
12_chapter 6.pdf1.47 MBAdobe PDFView/Open
13_conclusion and future work.pdf31.35 kBAdobe PDFView/Open
14_references.pdf528.71 kBAdobe PDFView/Open
15_list of publication.pdf75.55 kBAdobe PDFView/Open


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