Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/181318
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DC FieldValueLanguage
dc.coverage.spatialInformation and Communication Engineering
dc.date.accessioned2017-11-16T06:24:57Z-
dc.date.available2017-11-16T06:24:57Z-
dc.identifier.urihttp://hdl.handle.net/10603/181318-
dc.description.abstractAbstract available
dc.format.extentxix, 115p.
dc.languageEnglish US
dc.relation110-114
dc.rightsuniversity
dc.titleFPGA implementation of AES using montgomery multiplier and 2D DWT processor for secure image encoding
dc.title.alternative
dc.creator.researcherA, Dattathreya K
dc.subject.keywordEncoding
dc.subject.keywordMontgomery
dc.subject.keywordOrganization
dc.subject.keywordSecure
dc.subject.keywordStandards
dc.description.noteData not available
dc.contributor.guideKashwan, K R
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.date.registeredn.d.
dc.date.completed2016
dc.date.awardedn.d.
dc.format.dimensions30cm.
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File23.08 kBAdobe PDFView/Open
02_certificate.pdf784.68 kBAdobe PDFView/Open
03_abstract.pdf10.08 kBAdobe PDFView/Open
04_acknowledgement.pdf4.49 kBAdobe PDFView/Open
05_table of content.pdf14.52 kBAdobe PDFView/Open
06_list of table.pdf7.05 kBAdobe PDFView/Open
07_list of figures.pdf11.1 kBAdobe PDFView/Open
08_list of abbreviation.pdf6.34 kBAdobe PDFView/Open
09_chapter 1.pdf115.98 kBAdobe PDFView/Open
10_chapter 2.pdf281.49 kBAdobe PDFView/Open
11_chapter 3.pdf599.22 kBAdobe PDFView/Open
12_chapter 4.pdf1.26 MBAdobe PDFView/Open
13_conclusion and future scope.pdf48.56 kBAdobe PDFView/Open
14_references.pdf39.01 kBAdobe PDFView/Open
15_list of publication.pdf7.87 kBAdobe PDFView/Open


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