Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/181318
Title: FPGA implementation of AES using montgomery multiplier and 2D DWT processor for secure image encoding
Researcher: A, Dattathreya K
Guide(s): Kashwan, K R
Keywords: Encoding
Montgomery
Organization
Secure
Standards
University: Anna University
Completed Date: 2016
Abstract: Abstract available
Pagination: xix, 115p.
URI: http://hdl.handle.net/10603/181318
Appears in Departments:Faculty of Information and Communication Engineering

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01_title page.pdfAttached File23.08 kBAdobe PDFView/Open
02_certificate.pdf784.68 kBAdobe PDFView/Open
03_abstract.pdf10.08 kBAdobe PDFView/Open
04_acknowledgement.pdf4.49 kBAdobe PDFView/Open
05_table of content.pdf14.52 kBAdobe PDFView/Open
06_list of table.pdf7.05 kBAdobe PDFView/Open
07_list of figures.pdf11.1 kBAdobe PDFView/Open
08_list of abbreviation.pdf6.34 kBAdobe PDFView/Open
09_chapter 1.pdf115.98 kBAdobe PDFView/Open
10_chapter 2.pdf281.49 kBAdobe PDFView/Open
11_chapter 3.pdf599.22 kBAdobe PDFView/Open
12_chapter 4.pdf1.26 MBAdobe PDFView/Open
13_conclusion and future scope.pdf48.56 kBAdobe PDFView/Open
14_references.pdf39.01 kBAdobe PDFView/Open
15_list of publication.pdf7.87 kBAdobe PDFView/Open
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