Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/180794
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DC FieldValueLanguage
dc.coverage.spatialElectronics and Communication Engineering
dc.date.accessioned2017-11-13T10:46:46Z-
dc.date.available2017-11-13T10:46:46Z-
dc.identifier.urihttp://hdl.handle.net/10603/180794-
dc.description.abstractAvailable Abstract
dc.format.extentn.d.
dc.languageEnglish
dc.relation-
dc.rightsuniversity
dc.titleDesign of reduced complexity SQRT csla adder based bi recoder multiplier for digital fir filter
dc.title.alternative-
dc.creator.researcherM,Gnanasekaran
dc.subject.keywordDesign
dc.subject.keywordfilter
dc.subject.keywordrecoder
dc.subject.keywordSQRT
dc.description.noteReference given
dc.contributor.guideM, Manikandan
dc.publisher.placeChennai
dc.publisher.universitySt. Peters University
dc.publisher.institutionDepartment of Electronics and Communication
dc.date.registeredn.d
dc.date.completed2016
dc.date.awardedn.d
dc.format.dimensions-
dc.format.accompanyingmaterialNone
dc.type.degreePh.D.
dc.source.inflibnetINFLIBNET
Appears in Departments:Department of Electronics and Communication

Files in This Item:
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01_title.pdfAttached File30.82 kBAdobe PDFView/Open
02_certificate.pdf7.63 kBAdobe PDFView/Open
03_declaration.pdf7.64 kBAdobe PDFView/Open
04_acknowledgement.pdf8.43 kBAdobe PDFView/Open
05_abstract.pdf8.27 kBAdobe PDFView/Open
06_contents.pdf34.74 kBAdobe PDFView/Open
07_chapter 1.pdf186.71 kBAdobe PDFView/Open
08_chapter 2.pdf49.17 kBAdobe PDFView/Open
09_chapter 3.pdf710.72 kBAdobe PDFView/Open
10_chapter 4.pdf572.19 kBAdobe PDFView/Open
11_chapter 5.pdf1.13 MBAdobe PDFView/Open
12_chapter 6.pdf2.58 MBAdobe PDFView/Open
13_chapter 7.pdf10.18 kBAdobe PDFView/Open
14_references.pdf33.19 kBAdobe PDFView/Open


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