Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/179282
Title: Studies in layout driven routing thermal problems and delay fault classification for VLSI physical design
Researcher: Majumder, Subhashis
Guide(s): Bhattacharya, Bhargab B. and Das, Debesh K.
Keywords: Computer networks
Electronic circuit design
Floor planning
Global routing
Heuristics
Integrated circuits -- Very large scale integration -- Design
Network flow
Routing (Computer network management)
Stuck-at fault
University: Jadavpur University
Completed Date: 2005
Abstract: None newline
Pagination: vi, 131 p.
URI: http://hdl.handle.net/10603/179282
Appears in Departments:Department of Computer Science and Engineering

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01_title.pdfAttached File23.19 kBAdobe PDFView/Open
02_certificate.pdf181.64 kBAdobe PDFView/Open
03_dedication.pdf56.83 kBAdobe PDFView/Open
04_acknowledgment.pdf99.37 kBAdobe PDFView/Open
05_abstract.pdf57.17 kBAdobe PDFView/Open
06_list of publication.pdf204.56 kBAdobe PDFView/Open
07_content.pdf107.01 kBAdobe PDFView/Open
08_list of figures & tables.pdf150.86 kBAdobe PDFView/Open
09_chapter 1.pdf208.93 kBAdobe PDFView/Open
10_chapter 2.pdf634.65 kBAdobe PDFView/Open
11_chapter 3.pdf513.21 kBAdobe PDFView/Open
12_chapter 4.pdf342.97 kBAdobe PDFView/Open
13_chapter 5.pdf479.01 kBAdobe PDFView/Open
14_chapter 6.pdf232.75 kBAdobe PDFView/Open
15_chapter 7.pdf326.74 kBAdobe PDFView/Open
16_chapter 8.pdf141.71 kBAdobe PDFView/Open
17_bibliography.pdf186.72 kBAdobe PDFView/Open
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