Investigations on techniques to Improve the performance of phase Frequency detector and chargepump Of phase locked loop

Abstract

In recent years the mobile communication market has been newlinegrowing rapidly Frequency Synthesis clock and data recovery amplitude newlineand frequency demodulation etc are the major roles of Phase Locked Loop newlinePLL in mobile communication One of the challenges in PLL design is newlinereducing the acquisition time the time needed for a PLL to lock to the newlinefrequency and phase of a harmonic reference The faster a PLL can acquire newlinelock to a new frequency the faster the system can be made to operate newlineDesigning a frequency synthesizer having low settling time is a challenge in newlinethe mixedsignal circuit design area The Phase Frequency Detector PFD newlineand Charge Pump CP are the major blocks of a Charge Pump PLL CPPLL newlinewhich decides it s settling time The magnitude of frequency step of a newlinePFD decides the settling time of a PLL Larger the frequency step less will newlinebe the settling time of the PL newline newline