Investigation on performance of hybrid CMC dstatcom for mitigation of load current harmonics in medium voltage distribution network

Abstract

This thesis proposes the modeling and analysis of Static newlinesynchronous Compensator (DSTATCOM) systems utilizing Cascaded- newlineMultilevel Converters (CMCs). Among Flexible AC Transmission System newline(FACTS) controllers, the DSTATCOM has shown feasibility in terms of costeffectiveness newlinein a wide range of problem-solving abilities from transmission newlineto distribution levels. Referring to the literature reviews, the CMC with newlineseparated DC capacitors is clearly the most feasible topology for use as a newlinepower converter in the DSTATCOM applications. newlineThe controls for the CMC-based DSTATCOM were, however are newlinevery complicated. In-order to operate in a high-voltage application, a large newlinenumber of DC capacitors are utilized in a CMC-based DSTATCOM. All DC newlinecapacitor voltages must be balanced in order to avoid over-voltages on any newlineparticular link. These uneven DC voltages introduce voltage stress on the newlinesemiconductor switches, and also lower the quality of the synthesized output newlinewaveforms of the converter. newlinePrevious researches into DC capacitor voltage-balancing newlinetechniques were very straightforward, in that individual voltage compensators were added into the main control loop. However, the compensator design for newlinethese individual loops is very challenging because of the complexity of the newlinevoltage-loop transfer functions. Basically, the trial and error methods are used newlinefor the compensator design which is very complicated for the system with newlinegreater number of voltage levels. As a result, this approach potentially newlinereduces the reliability of the controller. The goal of this thesis is to provide, high-performance, reliable, newlineflexible, cost-effective power stages and controllers for the CMC-based newlineDSTATCOM. Major contributions done in this thesis are given as follows: newline1)Optimized design for the CMC-based DSTATCOM power stages and newlinepassive components, 2) Accurate models of the CMC for reactive power newlinecompensations in both abc and dqo coordinates, 3) DC-link balancing newlinestrategies, 4) Improvements in the CMC topology and 5) Analysis of various newlineCMC topology.