FPGA Based Novel Implementation of FIR Filter using Improved Reconfigurable Distributed Arithmetic Algorithm for Efficient Communication Application

Abstract

Research work focuses on the development of the Improved Reconfigurable Distributed Arithmetic architecture based Finite Impulse Response filter and its implementation for updown frequency converters in communication systems Traditional DSP based FIR filter implementation constituted MAC unit Multiplier implementation on FPGA essentially requires large chip area with increased power consumption reduction in throughput with increase in number of filter tap filter length resulting in reduction of sampling rate newline