1. Shodhganga@INFLIBNET
  2. Sri Chandrasekharendra Saraswathi Viswa Mahavidyalaya
  3. Department of Electronics & Communications Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/148501
Title: efficient implementation of AES using FPGA for high secure computing
Researcher: Senthil Kumar M
Guide(s): Rajalakshmi, S
Keywords: Advanced Encryption Standard
Field programmable gate array
Secure computing
University: Sri Chandrasekharendra Saraswathi Viswa Mahavidyalaya
Completed Date: 2015
Abstract: File attached
Pagination: 147 p.
URI: http://hdl.handle.net/10603/148501
Appears in Departments:Department of Electronics & Communications Engineering

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File Description SizeFormat 
01_title.pdfAttached File254.49 kBAdobe PDFView/Open
02_certiifcate.pdf165.8 kBAdobe PDFView/Open
03-declaration.pdf163.74 kBAdobe PDFView/Open
04_acknowledgement.pdf12.2 kBAdobe PDFView/Open
05_abstract.pdf11.67 kBAdobe PDFView/Open
06_content.pdf30.16 kBAdobe PDFView/Open
07_table.pdf12 kBAdobe PDFView/Open
08_figurer.pdf187.39 kBAdobe PDFView/Open
09_abbreviation.pdf100.15 kBAdobe PDFView/Open
10_chapter 1.pdf689.76 kBAdobe PDFView/Open
11_chapter 2.pdf194.65 kBAdobe PDFView/Open
12_chapter 3.pdf834.1 kBAdobe PDFView/Open
13_chapter 4.pdf848.44 kBAdobe PDFView/Open
14_chapter 5.pdf1.69 MBAdobe PDFView/Open
15_chapter 6.pdf2.13 MBAdobe PDFView/Open
16_chapter 7.pdf224.85 kBAdobe PDFView/Open
17_reference.pdf167.2 kBAdobe PDFView/Open
18_publication.pdf246.05 kBAdobe PDFView/Open
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