Some investigations on switching activities of high speed low power multiplier for integrated circuit applications

Abstract

The CMOS technology has paved the way to design, develop and implement more complicated signal processing systems on a VLSI chip in the recent years. In multiplier, the power consumption is directly proportional to number of switching activities. The main functions of a multiplier are partial product generation and summation. Hence the present research has been focused on design of multipliers to reduce the amount of power consumption by reducing the partial products. It is observed from the device level simulation using TANNER 12.6 EDA tool that the power consumption of the developed multiplier is reduced by 87% and 73% compared with conventional array and Booth multiplier in 0.13and#956;m technology. In this research work, the power consumption of the MAC unit was reduced using the pixel reusability technique and minimized the unwanted operation of the adder and multiplier unit to reduce the power consumption. By comparing the results the power consumption of MAC with repeated pixel values consideration are reduced by 16% compared to MAC without repeated pixel values consideration. The results show that the developed adder cell consumes less power in all operating voltage ranges. The design and implementation of high throughput FIR filter with low complexity and reduced switching activity is carried out. In the FIR filter operation, the two analysis has been done using different types of multipliers as array multiplier, Booth multiplier and hybrid multiplier and the second analysis is with and without repeated coefficient consideration. The comparative results show that the developed FIR filter with hybrid multiplier provides better power saving compared with Booth and array multiplier. FIR filter with coefficient reusability technique saves 19% of power than without coefficient reusability technique. newline newline newline