Optimization of wrapper design test access mechanism and test scheduling for embedded cores

Abstract

Electronic applications are currently developed under reuse-based design paradigm. The availability of high level integration leads to building of millions of gates System-on-Chip (SoC). Shortened production cycles, and increasing complexity of modern electronic systems have forced designers to employ reuse-based designs approaches. The SoC is one such example where pre-designed, pre-verified cores are integrated into a system. A lot of research work has been carried out and many researchers are working extensively to optimize the test length and fault coverage. The many factors that contribute to the overall problem can be broken down as follows: (a) low Test Access Port (TAP) bandwidth (b) limited embedded core accessibility (c) large volumes of test data (d) deep sub-micron effects not covered by standard fault models and (e) undefined Test Access Mechanism (TAM) structures. In this research work, process algebra, fuzzy terminology and Integer Linear Programming (ILP) based optimal solutions are proposed to obtain the above mentioned objectives. The objective of the first approach is to optimize wrapper cells because it has direct impact on hardware overhead, test time, and tester data volume. In this work, the wrapper which separates the core under test from other cores is assumed to be IEEE 1500-compliant. The results show much improved performance compared with Dynamic State Traversal (DST) method and in the range of 0.2% to 10%. The objective of second approach is to reduce test application time by proper test scheduling. The objective of the third approach is to achieve minimized test application time compared to second by test pipelining. Finally ILP was also used to get the optimized results of embedded core with power minimization as the objective. Finite State Machine (FSM) decomposition is applied to facilitate this approach. We find that in most cases, the static power savings are between 20% and 40%, while the dynamic power savings are between 10% and 30%. newline newline newline