Certain investigations on high throughput ldpc decoder architectures for ieee 802 16e standard

Abstract

Low Density Parity Check codesare forward error correcting codes newlineinvented by Gallager in 1963 and rediscovered by MacKay in 1999 Due to newlinethe inherent parallelism present in the decoding algorithm and excellent newlinecoding performance LDPC code has witnessed tremendous advances in newlinecommunication systems It is widely adopted in the communication standards newlinesuch as WLAN IEEE 802 11n WiMAX IEEE 80216e 10GBASE T newlineIEEE 802 3an and WPAN IEEE 802 15 3c An LDPC decoder is implemented as fully parallel and partially parallel architecture In spite of fully parallel architectures achieving high throughput they suffer from routing congestion and they are not scalable for newlinemultiple code lengths and code rates Partially parallel architectures have the newlineadvantages of scalable throughput easily configurable for multiple code newlinelengths and code rates Decoders of different parallelisms have various newlineperformances A decoder with higher parallelism achieves higher throughput newlineat the cost of larger area The advancements in the communication systems newlineneed a single decoder which supports multiple code lengths and rates newlineTherefore it is a challenge for designers to find good architecture which newlinefulfils the demands such as throughput area and multi code configurability newlineTherefore the present research concentrates on high throughput LDPC newlinedecoder architecture design with constraints on the requirements of higher newlinehardware utilization efficiency newline newline