Effects of noise on the performance of silicon nano wire transistors

Abstract

As the device size scaling continues many critical issues such as newlineincreased leakage current short-channel effects high-field effects variability newlinereliability noise and parasitic degrade the performance of the device Thus newlinesome of the above mentioned critical issues may be even more complicated newlinethat would give rise to new challenges in device engineering Therefore new newlinedevice structures and material innovation has attracted more attention as the newlineprimary enabler for performance enhancement in CMOS technology The newlineSilicon Nanowire Transistor SNWT is considered as one of the promising newlinecandidate for ultimate scaling due to its excellent electrostatic control newlinecapability improved transport property and feasible device design This kind newlineof device has the unique structural nature with quasi one dimensional and newlinestrongly confined nanowire channel three dimensional surrounding gatestack newlineof multiple crystallographic interface orientations and sharp transition newlinefrom the large source drain region to the narrow part of source drain newlineextension Moreover the fabrication of Nanowire is easy compared to CMOS newlinedevices Noise plays a vital role in determining the characteristics of the newlinedevice But the noise also increases as the dimension become smaller with newlinefewer and fewer charge carriers in active region of the device The most newlineimportant noise sources are the thermal noise and flicker noise Low newlinefrequency noise cannot be eliminated but with careful design of device and newlineinvolving suitable technology it can be substantially reduced newline newline