Investigation on design and implementation of arithmetic modules

Abstract

newlineThe increasing demand for portable electronic devices has led to emphasis on power consumption within the semiconductor industry Power is a problem when cooling and battery are a concern However there is no universal way to avoid tradeoffs between power delay and area and thus designers are required to choose appropriate techniques that satisfy application and product needs At the circuit level an optimized design is desired to avoid any degradation in the output voltage consume less power have less delay in critical path and be reliable even at low supply voltage as we scale towards deep sub micrometer A majority of portable multimedia and bio medical devices which meet the requirement of small size ultra low power are Digital Signal Processing DSP circuits interfacing with real world acting as personal aid devices. Speaking of DSP processors one of the main newlineprocessing bottlenecks is the Multiply and Accumulate unit MAC whose area and speed are the most important factors But increasing speed also increases the power consumption so there is an upper limit of speed for a given power criteria A fast and energy efficient multiplier is always needed in MAC of DSP image processing and arithmetic units in microprocessors contributing to the total power consumption of the system Considering the battery operated portable multimedia devices low power and fast designs of multipliers are more important than area Therefore the driving motivation for this research study is to investigate multiple architectures and circuit design techniques for arithmetic modules in MAC unit that are suitable to achieve low power consumption with high speed The design of a low power high speed multiplier architecture for a MAC unit and its implementation with power estimation is the goal of this thesis From the comparative analysis of the full adders for a supply voltage of 1 1v it is proved that the proposed adder shows an improvement of 37 3 percent in terms of power saving compared with static CMOS full adder in 90 nm at 20