Studies on various algorithmic improvements in non binary idpc decoder design

Abstract

Tremendous growth in the solid state electronics incorporates high volume of communication between digital machines The inculcation of modest error correction codes in a communication system are significant in satisfying the critical demand of data transfer and economical system design The effect of the coding reflects on the effectiveness of data transmission and efficiency of storage terminals Thus the choice of a suitable coding enhances the information transfer at any rate less than the channel capacity The main issue of channel coding is in finding a code which satisfies the required error correcting ability With the emerging growth of channel coding techniques next to Turbo codes LDPC codes find its position closer to Shannon s limit Low Density Parity Check LDPC code is a linear block code with good decoding performances and inherent parallelism in the algorithmic flow A Class of LDPC codes are defined in literature based on the elements of the parity check matrix and also based on its organization The parity check matrix can be defined to satisfy certain properties significant in decoding the code word with faster convergence and better decoding performance Another direction in the evolution of variations of LDPC is towards the optimization of these codes in hardware realization The structure of Non binary LDPC code with the elements of the parity check matrix defined over higher order Galois field put forth challenges in increasing the computation strength of the algorithm and hardware newlinecomplexity newline newline