1. Shodhganga@INFLIBNET
  2. Bharathiar University
  3. Department of Electronics and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/117930
Title: Certain investigations on the performance and hardware implementation of scheduling algorithms for packet switches in high speed networks
Researcher: Shanthi, G
Guide(s): Shanmugam, A
Keywords: Certain
Investigations
Hardware
Performance
Networks
University: Bharathiar University
Completed Date: 31/08/2006
Abstract: Abstract not available
Pagination: xvii, 142p.
URI: http://hdl.handle.net/10603/117930
Appears in Departments:Department of Electronics and Communication Engineering

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01_title page.pdfAttached File24.94 kBAdobe PDFView/Open
02_certificate.pdf31.07 kBAdobe PDFView/Open
03_declaration.pdf28 kBAdobe PDFView/Open
04_acknowledgement.pdf68.59 kBAdobe PDFView/Open
05_abstract.pdf118.12 kBAdobe PDFView/Open
06_table of content.pdf125.18 kBAdobe PDFView/Open
07_list of figures.pdf66.09 kBAdobe PDFView/Open
08_list of table.pdf31.56 kBAdobe PDFView/Open
09_list of abbreviation.pdf48.03 kBAdobe PDFView/Open
10_chapter 1.pdf440.02 kBAdobe PDFView/Open
11_chapter 2.pdf538.28 kBAdobe PDFView/Open
12_chapter 3.pdf502.28 kBAdobe PDFView/Open
13_chapter 4.pdf733.79 kBAdobe PDFView/Open
14_chapter 5.pdf592.95 kBAdobe PDFView/Open
15_chapter 6.pdf1.13 MBAdobe PDFView/Open
16_chapter 7.pdf187.16 kBAdobe PDFView/Open
17_appendix a.pdf103.17 kBAdobe PDFView/Open
18_appendix b.pdf187.45 kBAdobe PDFView/Open
19_references.pdf371.6 kBAdobe PDFView/Open
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