1. Shodhganga@INFLIBNET
  2. Bharathiar University
  3. Department of Electrical and Electronic Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/108818
Title: Development of new algorithms for test generation and simulation of stuck at faults in logic circuits
Researcher: Bhuvaneswari, M C
Guide(s): Sivanandam, S N
Keywords: Simulation
Generation
Development
Circuits
Algorithms
University: Bharathiar University
Completed Date: 31/10/2001
Abstract: Abstract available
Pagination: xix, 140p.
URI: http://hdl.handle.net/10603/108818
Appears in Departments:Department of Electrical and Electronic Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File32.26 kBAdobe PDFView/Open
02_declaration.pdf15.21 kBAdobe PDFView/Open
03_certificate.pdf29.43 kBAdobe PDFView/Open
04_acknowledgement.pdf49.74 kBAdobe PDFView/Open
05_abstract.pdf52.09 kBAdobe PDFView/Open
06_list of publication.pdf71.52 kBAdobe PDFView/Open
07_table of content.pdf95.33 kBAdobe PDFView/Open
08_list of table.pdf38.05 kBAdobe PDFView/Open
09_list of figures.pdf48.91 kBAdobe PDFView/Open
10_chapter 1.pdf363.06 kBAdobe PDFView/Open
11_chapter 2.pdf489.25 kBAdobe PDFView/Open
12_chapter 3.pdf930.37 kBAdobe PDFView/Open
13_chapter 4.pdf423.57 kBAdobe PDFView/Open
14_chapter 5.pdf685.37 kBAdobe PDFView/Open
15_chapter 6.pdf259.66 kBAdobe PDFView/Open
16_chapter 7.pdf214.16 kBAdobe PDFView/Open
17_summary and suggestions for further research.pdf132.22 kBAdobe PDFView/Open
18_reference books.pdf24.88 kBAdobe PDFView/Open
19_references.pdf481.81 kBAdobe PDFView/Open
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