Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/102429
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DC FieldValueLanguage
dc.coverage.spatialElectronics
dc.date.accessioned2016-07-04T11:49:02Z-
dc.date.available2016-07-04T11:49:02Z-
dc.identifier.urihttp://hdl.handle.net/10603/102429-
dc.description.abstractnewline Available
dc.format.extent28cm
dc.languageEnglish
dc.relationNO
dc.rightsuniversity
dc.titleLow Power Testing Techniques for VLSI Modules
dc.title.alternativeNo
dc.creator.researcherBalwinder Singh
dc.subject.keywordLow Power Testing Techniques
dc.subject.keywordVLSI Modules
dc.description.noteSummary: 141-144, References: 145-158
dc.contributor.guideNarang, Sukhleen Bindra
dc.publisher.placeAmritsar
dc.publisher.universityGuru Nanak Dev University
dc.publisher.institutionDepartment of Electronics Technology
dc.date.registered14/09/2009
dc.date.completed04/10/2013
dc.date.awarded28/08/2014
dc.format.dimensions158p.
dc.format.accompanyingmaterialCD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics Technology

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01_title.pdfAttached File62.02 kBAdobe PDFView/Open
02_certificate.pdf20.76 kBAdobe PDFView/Open
03_declaration.pdf17.47 kBAdobe PDFView/Open
04_acknowledgements.pdf24.77 kBAdobe PDFView/Open
05_abstract.pdf30.85 kBAdobe PDFView/Open
06_contents.pdf28.54 kBAdobe PDFView/Open
07_list of figures.pdf26.3 kBAdobe PDFView/Open
08_list of tables.pdf20.62 kBAdobe PDFView/Open
09_abbreviations.pdf20.84 kBAdobe PDFView/Open
10_thesis outcomes.pdf26.9 kBAdobe PDFView/Open
11_chapter 1.pdf452.32 kBAdobe PDFView/Open
12_chapter 2.pdf251.83 kBAdobe PDFView/Open
13_chapter 3.pdf2.68 MBAdobe PDFView/Open
14_chapter 4.pdf4.85 MBAdobe PDFView/Open
15_chapter 5.pdf874.86 kBAdobe PDFView/Open
16_chapter 6.pdf36.13 kBAdobe PDFView/Open
17_references.pdf97.3 kBAdobe PDFView/Open


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