Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/5633
Title: Studies on transparent conducting oxides for CdTe solar cell application
Researcher: Krishnakumar, V
Guide(s): Ramamurthi, K
Keywords: solar cell application
transparent conducting oxides
Solar Energy
Upload Date: 19-Dec-2012
University: Bharathidasan University
Completed Date: November 2008
Abstract: This thesis describes the studies on TCOs for CdTe solar cell application. Cadmium stannate thin films are prepared by spray pyrolysis technique using a set of new precursors (cadmium acetate and tin (II) chloride). Films prepared at substrate temperature of 450 °C are amorphous and films prepared at 500 °C produce Cd2SnO4 films in (111) hkl orientation in orthorhombic structure with resistivity of 35.6 x 10-4 and#937; cm. A new procedure of cover layer formation has been introduced to improve the electrical property of the film without affecting the optical and structural properties. The minimum resistivity of 6 and#61655;and#61472;10-4 and#937; cm was obtained for the films prepared with cover layer procedure. X-ray Photoelectron Spectroscopy (XPS) was used to study the CdS/ITO and CdS/SnO2/ITO interface properties with the help of XPS sputter depth profile technique. CdS/ITO interface studies show that indium is diffusing through CdS layer when the sample is treated with different heat treatments. But CdS/SnO2/ITO interfaces show that the SnO2 buffer layer acts as a barrier for the indium diffusion from ITO to CdS. Different post annealing treatments (vacuum annealing, air annealing and CdCl2 activation) on CdS/ITO and CdS/SnO2/ITO do not lead to considerable change in band offset in these interfaces. Results from the present study show that the valence band offsets are 1.25 and#61617;and#61472;0.1eV for the CdS/ITO and 1.5 and#61617;and#61472;0.1 eV for CdS/SnO2 interface, respectively. Solar cells prepared using ITO/SnO2 substrates with CdS layer thickness of ~140 nm yields efficiency and#951; = 9.5%. Reducing the CdS film thickness to ~60-70 nm results poor device performance with low efficiency (and#951; = 4.8%) due to the presence of pin holes. A new method of forming CdS double layer has been introduced to reduce the CdS film thickness and to avoid pinholes. In the case of double layer procedure, a thin CdS layer of ~50?60nm was deposited at standard substrate temperature of ~520 °C and the second layer of ~10-20nm was deposited at low substrate temperature of ~250 °C.
Pagination: 150p.
URI: http://hdl.handle.net/10603/5633
Appears in Departments:Department of Physics

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01_title.pdfAttached File251.8 kBAdobe PDFView/Open
02_dedication.pdf75.2 kBAdobe PDFView/Open
03_certificate.pdf205.46 kBAdobe PDFView/Open
04_certificate.pdf80.13 kBAdobe PDFView/Open
05_declaration.pdf131.97 kBAdobe PDFView/Open
06_acknowledgements.pdf138.42 kBAdobe PDFView/Open
07_abstract.pdf112.36 kBAdobe PDFView/Open
08_contents.pdf143.73 kBAdobe PDFView/Open
09_list of figures.pdf142.95 kBAdobe PDFView/Open
10_list of tables.pdf134.05 kBAdobe PDFView/Open
11_list of symbols.pdf136.27 kBAdobe PDFView/Open
12_chapter 1.pdf335.52 kBAdobe PDFView/Open
12_chapter 2.pdf422.41 kBAdobe PDFView/Open
14_chapter 3.pdf926.63 kBAdobe PDFView/Open
15_chapter 4.pdf886.38 kBAdobe PDFView/Open
16_chapter 5.pdf1.84 MBAdobe PDFView/Open
17_chapter 6.pdf1.29 MBAdobe PDFView/Open
18_chapter 7.pdf150.43 kBAdobe PDFView/Open
19_appendix.pdf1.45 MBAdobe PDFView/Open
20_references.pdf149.53 kBAdobe PDFView/Open
21_papers.pdf1.24 MBAdobe PDFView/Open


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