Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/49446
Full metadata record
DC FieldValueLanguage
dc.coverage.spatialInvestigations on performance Improvements of self biased Adaptive bandwidth PLLSen_US
dc.date.accessioned2015-09-11T05:33:44Z-
dc.date.available2015-09-11T05:33:44Z-
dc.date.issued2015-09-11-
dc.identifier.urihttp://hdl.handle.net/10603/49446-
dc.description.abstractThe present research work attempts a number of modifications of newlinethe well established self biased adaptive bandwidth Phase Locked Loop newline PLLs These modifications are considered in order to address the issues that newlinehave become important in the context of PLLs for multi core processors newlinewhich operate with progressively increasing speeds and reduced supply newlinevoltages In a multi core environment the processor clocks are switched newlinerapidly across different pairs of frequency and supply voltage settings in order newlineto maintain the lowest power envelope constraint This requirement newlinecombined with high operating frequencies thus demands faster settling times newlineaccompanied by lower jitter constraints on the PLL design Simultaneously newlinethe PLLs also feed increasing number of Delay Locked DLLs Loops and newlineclock networks hence the capture transients overshoot undershoot of these newlinePLL are required to be as minimum as possible Motivated by these evolving newlineConstraints the present work investigates alternative ways in which the newlinetraditional self biased PLL architecture can be modified to improve the newlineperformance with respect of jitter capture transients undershoot overshoot newlinesettling time and operating frequency range while retaining the inherent newlinebenefits of the traditional second order self biased adaptive bandwidth PLL newlinearchitecture To the best of this researcher s knowledge such studies of newlinerelative contributions to overall jitter or methods of their reduction have not newlinebeen reported in the literature in the context of self biased PLL s though newlinethese continue to be widely used for microprocessor clock generation newline newlineen_US
dc.format.extentxx, 106p.en_US
dc.languageEnglishen_US
dc.relationp103-105.en_US
dc.rightsuniversityen_US
dc.titleInvestigations on performance Improvements of self biased Adaptive bandwidth PLLSen_US
dc.title.alternativeen_US
dc.creator.researcherDhurga devi Jen_US
dc.subject.keywordDelay Locked Loopen_US
dc.subject.keywordMicroprocessor clock generationen_US
dc.subject.keywordPhase Locked Loopen_US
dc.description.notereference p103-105.en_US
dc.contributor.guideRamakrishna P Ven_US
dc.publisher.placeChennaien_US
dc.publisher.universityAnna Universityen_US
dc.publisher.institutionFaculty of Information and Communication Engineeringen_US
dc.date.registeredn.d,en_US
dc.date.completed01/08/2014en_US
dc.date.awarded30/08/2014en_US
dc.format.dimensions23cm.en_US
dc.format.accompanyingmaterialNoneen_US
dc.source.universityUniversityen_US
dc.type.degreePh.D.en_US
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File26.44 kBAdobe PDFView/Open
02_certificate.pdf528.16 kBAdobe PDFView/Open
03_abstract.pdf12.33 kBAdobe PDFView/Open
04_acknowledgement.pdf5.78 kBAdobe PDFView/Open
05_content.pdf37.37 kBAdobe PDFView/Open
06_chapter1.pdf22.17 kBAdobe PDFView/Open
07_chapter2.pdf548.01 kBAdobe PDFView/Open
08_chapter3.pdf233.52 kBAdobe PDFView/Open
09_chapter4.pdf450.18 kBAdobe PDFView/Open
10_chapter5.pdf820.71 kBAdobe PDFView/Open
11_chapter6.pdf15.56 kBAdobe PDFView/Open
12_reference.pdf12.76 kBAdobe PDFView/Open
13_publication.pdf5.21 kBAdobe PDFView/Open


Items in Shodhganga are protected by copyright, with all rights reserved, unless otherwise indicated.