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Title: Design of high speed reconfigurable co processor for next generation communication platform
Researcher: Mallikarjunaswamy S
Guide(s): Nataraj K R
Keywords: Data Transmission
Upload Date: 26-Aug-2015
University: Jain University
Completed Date: 11/07/2015
Abstract: There has been an increasing demand on the quality of data transmission and reception newlineAs a result there has been an increase in bandwidth on demand and quality of service These results in increase of data traffic which results in information loss accuracy reduction and reliability reduction A coprocessor is designed to overcome this drawback which can be used for communication operation which is highly reliable and more accurate with less delay The research high speed reconfigurable coprocessor can be easily implemented using various standard operations such as Bit shuffle operation convolutional encoding fast Fourier transform interleaving modulation scrambling Shift XOR array viterbi decoding and many other functions which make use of the research design newline newline
Pagination: 127 p.
Appears in Departments:Department of Electronics Engineering

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File Description SizeFormat 
01_title page.pdfAttached File122.85 kBAdobe PDFView/Open
02_certificate.pdf141.76 kBAdobe PDFView/Open
03_declaration.pdf141.87 kBAdobe PDFView/Open
04_acknowledgement.pdf148.03 kBAdobe PDFView/Open
05_abstract.pdf139.16 kBAdobe PDFView/Open
06_contents.pdf220.41 kBAdobe PDFView/Open
07_chapter 1.pdf1.28 MBAdobe PDFView/Open
08_chapter 2.pdf625.29 kBAdobe PDFView/Open
09_chapter 3.pdf1.46 MBAdobe PDFView/Open
10_chapter 4.pdf1.53 MBAdobe PDFView/Open
11_chapter 5.pdf618.46 kBAdobe PDFView/Open
12_chapter 6.pdf523.79 kBAdobe PDFView/Open
13_chapter 7.pdf3.02 MBAdobe PDFView/Open
14_chapter 8.pdf225.42 kBAdobe PDFView/Open
15_bibliography.pdf187.15 kBAdobe PDFView/Open

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