Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/382780
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dc.date.accessioned2022-05-27T06:49:25Z-
dc.date.available2022-05-27T06:49:25Z-
dc.identifier.urihttp://hdl.handle.net/10603/382780-
dc.description.abstractDigital Signal Processing systems are used for real-time and online-offline processing of pre-loaded data. The Residue Number System (RNS) is a carry-free system used in high-speed arithmetic components like digital signal processing, image processing, and cryptography. The RNS has three categories: (a) Forward Conversion (Binary to Residue Conversion), (b) Moduli channel (Selection of Moduli) (c) Reverse Conversion (Residue to Binary Conversion). The selection of moduli in an RNS-based DSP system significantly impacts the hardware complexity, power consumption, and speed. newlineModulo addition is used to perform the arithmetic operations in the RNS domain. In most RNS-based system designs, the moduli set is preferred. Several techniques to develop the efficient area-delay logic architectures for diminished-1 modulo adders have been proposed in the last decade. The diminished-1 modulo parallel prefix adder structure uses the pre-processing stage , sum computation stage , carry computation stage , and carry increment stage . Modulo multiplier offers higher computational speed than a standard multiplier. It is frequently used in data security and in residue number system design. The modulo multiplier has three basic blocks-partial product generation block, an inverted-end around carry adder tree block, and a diminished-1 modulo adder block. newlineThe main objective of this research work is to reduce the complexity of performing operations. The architecture, based on a parallel prefix tree is helpful for computation at a higher speed. The proposed parallel prefix tree adder improves the speed of multiplication. The reverse converter design consists of residue to binary conversion performed using the Chinese Remainder Theorem (CRT). The design for five moduli sets formulates the wide modular devaluation constrained by using the properties of the Chinese Remainder Theorem (CRT). The proposed works show the efficient designs of RNS based arithmetic circuits newline
dc.format.extentxv;120p.
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleDesign of RNS Based Efficient Arithmetic Circuits
dc.title.alternative
dc.creator.researcherPatel, Beerendra Kumar
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideKanungo, Jitendra
dc.publisher.placeGuna
dc.publisher.universityJaypee University of Engineering and Technology, Guna
dc.publisher.institutionDepartment of Electronics and Communication
dc.date.registered2015
dc.date.completed2021
dc.date.awarded2022
dc.format.dimensions
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Communication

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01-title.pdf.pdfAttached File439.07 kBAdobe PDFView/Open
02-certificate.pdf552.39 kBAdobe PDFView/Open
03-abstract.pdf.pdf516.31 kBAdobe PDFView/Open
04-declaration by the scholar.pdf435.63 kBAdobe PDFView/Open
05-acknowledgements.pdf454.71 kBAdobe PDFView/Open
06-contents.pdf.pdf851.17 kBAdobe PDFView/Open
07-list of tables.pdf693.25 kBAdobe PDFView/Open
08-list of figures.pdf566.1 kBAdobe PDFView/Open
09-list of acronyms and abbreviations.pdf438.45 kBAdobe PDFView/Open
10-chapter-1.pdf3.65 MBAdobe PDFView/Open
11-chapter-2.pdf2.33 MBAdobe PDFView/Open
12-chapter-3.pdf18.88 MBAdobe PDFView/Open
13-chapter-4.pdf18.19 MBAdobe PDFView/Open
14-chapter-5.pdf12.91 MBAdobe PDFView/Open
15-chapter-6.pdf17.57 MBAdobe PDFView/Open
16-chapter-7.pdf25.14 kBAdobe PDFView/Open
17-conclusion.pdf359.66 kBAdobe PDFView/Open
18-bibliography.pdf89.72 kBAdobe PDFView/Open
19-list of publications.pdf622.63 kBAdobe PDFView/Open
80_recommendation.pdf582.7 kBAdobe PDFView/Open


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