Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/337023
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2021-08-23T05:01:05Z-
dc.date.available2021-08-23T05:01:05Z-
dc.identifier.urihttp://hdl.handle.net/10603/337023-
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titlePower Aware Test Architecture for System on Chip
dc.title.alternative
dc.creator.researcherParmar, Harikrushna
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.subject.keywordSystem on Chip
dc.subject.keywordVLSI
dc.description.note
dc.contributor.guideMehta, Usha
dc.publisher.placeAhmedabad
dc.publisher.universityNirma University
dc.publisher.institutionInstitute of Technology
dc.date.registered2013
dc.date.completed2020
dc.date.awarded2021
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Institute of Technology

Files in This Item:
File Description SizeFormat 
10. list of table.pdfAttached File53.43 kBAdobe PDFView/Open
11. list of algorithm.pdf48.67 kBAdobe PDFView/Open
12. list of abreviation.pdf46.22 kBAdobe PDFView/Open
13. chapter-1.pdf1.85 MBAdobe PDFView/Open
14. chapter-2.pdf620.74 kBAdobe PDFView/Open
15. chapter-3.pdf475.12 kBAdobe PDFView/Open
16. chapter-4.pdf617.18 kBAdobe PDFView/Open
17. conclusion.pdf65.93 kBAdobe PDFView/Open
18. bibliography.pdf100.14 kBAdobe PDFView/Open
1. title.pdf223.09 kBAdobe PDFView/Open
2. dedication.pdf26.19 kBAdobe PDFView/Open
3. certificate.pdf45.68 kBAdobe PDFView/Open
4. declaration.pdf54.18 kBAdobe PDFView/Open
5. publication.pdf56.75 kBAdobe PDFView/Open
6. absract.pdf49.36 kBAdobe PDFView/Open
7. acknowledgement.pdf46.74 kBAdobe PDFView/Open
80_recommendation.pdf70.11 kBAdobe PDFView/Open
8. content.pdf76.23 kBAdobe PDFView/Open
9. list of figure.pdf105.51 kBAdobe PDFView/Open


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