Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/337023
Title: Power Aware Test Architecture for System on Chip
Researcher: Parmar, Harikrushna
Guide(s): Mehta, Usha
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
System on Chip
VLSI
University: Nirma University
Completed Date: 2020
Pagination: 
URI: http://hdl.handle.net/10603/337023
Appears in Departments:Institute of Technology

Files in This Item:
File Description SizeFormat 
10. list of table.pdfAttached File53.43 kBAdobe PDFView/Open
11. list of algorithm.pdf48.67 kBAdobe PDFView/Open
12. list of abreviation.pdf46.22 kBAdobe PDFView/Open
13. chapter-1.pdf1.85 MBAdobe PDFView/Open
14. chapter-2.pdf620.74 kBAdobe PDFView/Open
15. chapter-3.pdf475.12 kBAdobe PDFView/Open
16. chapter-4.pdf617.18 kBAdobe PDFView/Open
17. conclusion.pdf65.93 kBAdobe PDFView/Open
18. bibliography.pdf100.14 kBAdobe PDFView/Open
1. title.pdf223.09 kBAdobe PDFView/Open
2. dedication.pdf26.19 kBAdobe PDFView/Open
3. certificate.pdf45.68 kBAdobe PDFView/Open
4. declaration.pdf54.18 kBAdobe PDFView/Open
5. publication.pdf56.75 kBAdobe PDFView/Open
6. absract.pdf49.36 kBAdobe PDFView/Open
7. acknowledgement.pdf46.74 kBAdobe PDFView/Open
80_recommendation.pdf70.11 kBAdobe PDFView/Open
8. content.pdf76.23 kBAdobe PDFView/Open
9. list of figure.pdf105.51 kBAdobe PDFView/Open
Show full item record


Items in Shodhganga are protected by copyright, with all rights reserved, unless otherwise indicated.

Altmetric Badge: