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Title: Digital filter design using evolvable Hardware chip for image Enhancement
Researcher: Sumathi A
Guide(s): Wahida banu R S D
Keywords: Image enhancement
Relevant processing
Upload Date: 27-Nov-2014
University: Anna University
Completed Date: 01/05/2008
Abstract: Image enhancement is an important image preprocessing technique newlineand it allows an encoded image to be reconstructed progressively in newlineterms of fidelity detail or resolution Specific Regions of Interest newlinecan also be specified and encoded with greater detail Random access newlineto the compressed image is possible allowing certain areas to be newlinedecoded without the need to decode the entire image While some newlineapplications such as enhancing poor quality satellite images will require newlineimage enhancement to be implemented in software other image enhancement newlineschemes to be ported inside a digital camera for example will require the newlinealgorithm to be implemented in hardware A hybrid coprocessing newlineapproach is also possible using hardware for parts of the newlinealgorithm that are computationally intensive and software for the parts that newlineare difficult to implement in a hardware environment newlineIn this thesis a VHDL implementation of the image enhancement newlinefilter is presented suitable for implementation on an FPGA In the first phase newlineof this work the design presented has been verified in simulation The newlinesecond phase involves programming an FPGA with these VHDL modules for newlinecomplete system integration The VHDL hardware description language is newlineused to develop digital designs that can perform this relevant processing The newlineVHDL implementation once programmed into the FPGA is intended newlineto replace that part of the software implementation It is estimated that newlinewhen implemented in hardware the VHDL module GA processor VRC newlinecould perform its computation approximately 180 times faster compared to newlinethe time taken by conventional image enhancement filters newline newline
Pagination: xviii, 151p.
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File21.65 kBAdobe PDFView/Open
02_abstract.pdf11.02 kBAdobe PDFView/Open
03_acknowledgement.pdf6.43 kBAdobe PDFView/Open
04_content.pdf34.7 kBAdobe PDFView/Open
05_chapter1.pdf104.59 kBAdobe PDFView/Open
06_chapter2.pdf521.84 kBAdobe PDFView/Open
07_chapter3.pdf165.21 kBAdobe PDFView/Open
08_chapter4.pdf1.04 MBAdobe PDFView/Open
09_chapter5.pdf2.7 MBAdobe PDFView/Open
10_chapter6.pdf29.36 kBAdobe PDFView/Open
11_appendix.pdf68.35 kBAdobe PDFView/Open
12_reference.pdf42.04 kBAdobe PDFView/Open
13_publication.pdf16.13 kBAdobe PDFView/Open
14_vitae.pdf11.65 kBAdobe PDFView/Open

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