Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/286309
Title: Performance analysis and benchmarking of tunnel transistors with circuit co design for energy efficient and reliable computing architectures
Researcher: Shaik, Sadulla
Guide(s): Rama Krishna K
Keywords: Complementary Metal Oxide Semiconductor
Engineering
Engineering and Technology
Engineering Electrical and Electronic
Integrated Circuit
Reliable Computing Architectures
Tunnel Field Effect Transistors
Tunnel Transistors
University: Acharya Nagarjuna University
Completed Date: 2017
Abstract: file attached
Pagination: 153 p.
URI: http://hdl.handle.net/10603/286309
Appears in Departments:Department of Education

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File107.19 kBAdobe PDFView/Open
02_declaration.pdf97.33 kBAdobe PDFView/Open
03_certificate.pdf94.06 kBAdobe PDFView/Open
04_acknowledgements.pdf99.8 kBAdobe PDFView/Open
05_abstract.pdf92.15 kBAdobe PDFView/Open
06_contents.pdf226.44 kBAdobe PDFView/Open
07_chapter 1.pdf681.71 kBAdobe PDFView/Open
08_chapter 2.pdf78.9 kBAdobe PDFView/Open
09_chapter 3.pdf158.78 kBAdobe PDFView/Open
10_chapter 4.pdf245.28 kBAdobe PDFView/Open
11_chapter 5.pdf312.11 kBAdobe PDFView/Open
12_chapter 6.pdf218.11 kBAdobe PDFView/Open
13_chapter 7.pdf102.49 kBAdobe PDFView/Open
14_bibliography.pdf457.71 kBAdobe PDFView/Open
15_publications.pdf32.68 kBAdobe PDFView/Open


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