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Title: Implementation of novel low power VLIW DSP architecture
Researcher: Seshasayanan R
Guide(s): Srivatsa S K
Keywords: Application specific instruction set processor
Clock skew problem
Dynamic voltage scaling
Upload Date: 17-Nov-2014
University: Anna University
Completed Date: 01/10/2007
Abstract: Technology has seen the development of processor industry right newlinefrom micro to the latest Nano technology With Speed and performance newlinebeing important criteria not much attention has been given to the power newlinerequirement for these integrated circuits With gaining popularity in newlineapplication specific instruction set processor ASIP developing ASIP newlineprocessors has gained popularity since these processors possess unique newlineproperties like low power consumption and dissipation There are two newlinetechniques adopted for the low power design namely altering the voltage of newlinethe processor and the other one is designing the processor in asynchronous newlineway to further reduce the power and clock skew problem newlineA small but growing number of processors have the ability to newlinedynamically change the CPU voltage level without rebooting and this is newlineknown as dynamic voltage scaling DVS there by consuming less power and newlineless energy newline newline
Pagination: xviii, 136p.
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File36.62 kBAdobe PDFView/Open
02_certificate.pdf5.69 kBAdobe PDFView/Open
03_abstract.pdf13.61 kBAdobe PDFView/Open
04_acknowledgement.pdf6.49 kBAdobe PDFView/Open
05_content.pdf25.61 kBAdobe PDFView/Open
06_chapter1.pdf168.48 kBAdobe PDFView/Open
07_chapter2.pdf137.35 kBAdobe PDFView/Open
08_chapter3.pdf497.63 kBAdobe PDFView/Open
09_chapter4.pdf248.99 kBAdobe PDFView/Open
10_chapter5.pdf378.76 kBAdobe PDFView/Open
11_chapter6.pdf24.47 kBAdobe PDFView/Open
12_reference.pdf62.2 kBAdobe PDFView/Open
13_publication.pdf6.75 kBAdobe PDFView/Open
14_vitae.pdf5.52 kBAdobe PDFView/Open

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