Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/18806
Title: Memory customization in multiprocessor Systems-On-Chip
Researcher: Mittal, Shaily
Guide(s): Nitin
Keywords: Embedded Systems
Multiprocessor
Systems-On-Chip
Upload Date: 30-May-2014
University: Jaypee University of Information Technology, Solan
Completed Date: 19/04/2014
Abstract: With the change in time, there is increase in the demand of embedded system applications with advanced technologies. Multiprocessor Systems-on-Chip (MPSoC s) become usual in embedded systems to provide required power efficient systems. The power consumed and performance of the system majorly depends on the memory organization of the system and hence requiring system with low power memory organizations. The aim of this dissertation is to find solutions of various issues involved in cache memory design with respect to shared and private memory systems being used by multiple processors. newlineThe first issue is multiple processor synchronization. This problem generally occurs in case of shared memory. A semaphore solution with the intent of decreasing energy consumption and cache miss rate is proposed to solve the problem of synchronization among processors in shared memory architecture. The second issue is the use of replacement policies in SPM. The use of Scratch pad memory with three different replacement policies FIFO, LRU and Random have been proposed which has been never done earlier. newlineThe third major problem is the need of a simulator which provides the shared memory environment for multiprocessors. So, in this thesis, a Memory Map simulator having multiprocessors with shared memory architecture is designed. Memory Map is a simulator which can simulate system having multiple processors with shared and private caches configuration. The metrics cache miss rate and cache hit rate can be evaluated using this simulator. In this simulator, user can reconfigure cache memory and can also alter the number of processors within the application program.
Pagination: 157p.
URI: http://hdl.handle.net/10603/18806
Appears in Departments:Department of Computer Science Engineering

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01_title.pdfAttached File88.57 kBAdobe PDFView/Open
02_certificate.pdf89.82 kBAdobe PDFView/Open
03_acknowledgement.pdf144.13 kBAdobe PDFView/Open
04_contents.pdf459.19 kBAdobe PDFView/Open
05_list of table & figures.pdf1.05 MBAdobe PDFView/Open
06_chapter 1.pdf2.99 MBAdobe PDFView/Open
07_chapter 2.pdf1.57 MBAdobe PDFView/Open
08_chapter 3.pdf1.68 MBAdobe PDFView/Open
09_chapter 4.pdf2.83 MBAdobe PDFView/Open
10_chapter 5.pdf3.5 MBAdobe PDFView/Open
11_chapter 6.pdf1.2 MBAdobe PDFView/Open
12_chapter 7.pdf2.43 MBAdobe PDFView/Open
13_chapter 8.pdf1.67 MBAdobe PDFView/Open
14_chapter 9.pdf1.42 MBAdobe PDFView/Open
15_chapter 10.pdf4.15 MBAdobe PDFView/Open
16_chapter 11.pdf601.32 kBAdobe PDFView/Open
17_references.pdf2.88 MBAdobe PDFView/Open


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