Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/8623
Title: Design and synthesis of efficient MAC architectures for high speed decimal processor
Researcher: James, Rekha K
Guide(s): Jacob, K Poulose
Keywords: Computer Sciences
High speed decimal processor
Upload Date: 7-May-2013
University: Cochin University of Science and Technology
Completed Date: 04/01/2010
Pagination: 224p.
URI: http://hdl.handle.net/10603/8623
Appears in Departments:Department of Computer Science

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File139.25 kBAdobe PDFView/Open
02_certificate & declarations.pdf117.16 kBAdobe PDFView/Open
03_acknowledgements.pdf99.92 kBAdobe PDFView/Open
04_abstract.pdf146.92 kBAdobe PDFView/Open
05_contents.pdf104.67 kBAdobe PDFView/Open
06_list of figures tables & abbreviations.pdf183.34 kBAdobe PDFView/Open
07_chapter 1.pdf566.32 kBAdobe PDFView/Open
08_chapter 2.pdf1.17 MBAdobe PDFView/Open
09_chapter 3.pdf463.19 kBAdobe PDFView/Open
10_chapter 4.pdf1.82 MBAdobe PDFView/Open
11_chapter 5.pdf276.73 kBAdobe PDFView/Open
12_chapter 6.pdf1.97 MBAdobe PDFView/Open
13_chapter 7.pdf255.64 kBAdobe PDFView/Open
14_references.pdf387.42 kBAdobe PDFView/Open
15_list of publications.pdf150.04 kBAdobe PDFView/Open
16_appendix.pdf7.54 MBAdobe PDFView/Open


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