Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/81909
Title: Implementation and analysis of coordination techniques for scheduling configurable computation hardware blocks in fpga at run time
Researcher: Bharathi, N
Guide(s): Neelamegam, P
Keywords: Various Design Levels
University: SASTRA University
Completed Date: 31/10/2013
Abstract: Abstract included newline
Pagination: xix, 149
URI: http://hdl.handle.net/10603/81909
Appears in Departments:School of Computing

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01_tittle.pdfAttached File46.03 kBAdobe PDFView/Open
02_certificate.pdf15.21 kBAdobe PDFView/Open
03_declaration.pdf17.05 kBAdobe PDFView/Open
04_dedications.pdf18.65 kBAdobe PDFView/Open
05_acknowledgements.pdf25.79 kBAdobe PDFView/Open
06_table_of_contents.pdf31.73 kBAdobe PDFView/Open
07_list_of_tables.pdf16.61 kBAdobe PDFView/Open
08_list_of_figures.pdf31.16 kBAdobe PDFView/Open
09_abstract.pdf19.05 kBAdobe PDFView/Open
10_chapter_01.pdf41.24 kBAdobe PDFView/Open
11_chapter_02.pdf104.38 kBAdobe PDFView/Open
12_chapter_03.pdf671.17 kBAdobe PDFView/Open
13_chapter_04.pdf919.82 kBAdobe PDFView/Open
14_chapter_05.pdf707.88 kBAdobe PDFView/Open
15_chapter_06.pdf19.21 kBAdobe PDFView/Open
16_references.pdf110.41 kBAdobe PDFView/Open
17_appendix.pdf2.31 MBAdobe PDFView/Open


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