Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/72468
Title: Design validation and FPGA implementation of multistage telecommunication networks in HDL environment
Researcher: Kumar, Adesh
Guide(s): Kuchhal, Piyush and Singhal, Sonal
Keywords: Design
FPGA implementation
HDL environment
University: University of Petroleum and Energy Studies (UPES)
Completed Date: 2014
Abstract: Abstract available newline
Pagination: 201p.
URI: http://hdl.handle.net/10603/72468
Appears in Departments:Department of Electrical Engineering

Files in This Item:
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01_title.pdfAttached File106.58 kBAdobe PDFView/Open
02_certificate.pdf102.83 kBAdobe PDFView/Open
03_acknowledgements.pdf84.43 kBAdobe PDFView/Open
04_curriculam vitae.pdf120.52 kBAdobe PDFView/Open
05_abstract.pdf86.85 kBAdobe PDFView/Open
06_summary.pdf96.32 kBAdobe PDFView/Open
07_contents.pdf87.12 kBAdobe PDFView/Open
08_list of figures.pdf101.28 kBAdobe PDFView/Open
09_list of tables.pdf93.9 kBAdobe PDFView/Open
10_acronyms.pdf94.57 kBAdobe PDFView/Open
11_list of abbrevations.pdf82.17 kBAdobe PDFView/Open
12_chapter-1.pdf336.37 kBAdobe PDFView/Open
13_chapter-2.pdf630.12 kBAdobe PDFView/Open
14_chapter-3.pdf1.71 MBAdobe PDFView/Open
15_chapter-4.pdf965.53 kBAdobe PDFView/Open
16_chapter-5.pdf791.23 kBAdobe PDFView/Open
17_chapter-6.pdf3.74 MBAdobe PDFView/Open
18_chapter-7.pdf162.64 kBAdobe PDFView/Open
19_appendix.pdf356.74 kBAdobe PDFView/Open


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