Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/6521
Title: VLSI design of low power digital FIR filter using PSPICE and VLSI design of high speed digital FIR filter using VERILOG HDL
Researcher: Vigneswaran T
Guide(s): Malarvizhi, S
Keywords: Electronics and Communication
VLSI
PSPICE
VERILOG HDL
Upload Date: 18-Jan-2013
University: SRM University
Completed Date: November, 2008
Abstract: Included
Pagination: --
URI: http://hdl.handle.net/10603/6521
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File15.04 kBAdobe PDFView/Open
02_certificate & declarations.pdf9.83 kBAdobe PDFView/Open
03_acknowledgement & abstract.pdf15.1 kBAdobe PDFView/Open
04_contents.pdf17.04 kBAdobe PDFView/Open
05_list of tables fgures & abbreviations.pdf24.27 kBAdobe PDFView/Open
06_part i_chapter 1.pdf16.17 kBAdobe PDFView/Open
07_chapter 2.pdf12.51 kBAdobe PDFView/Open
08_chapter 3.pdf21.39 kBAdobe PDFView/Open
09_chapter 4.pdf79.05 kBAdobe PDFView/Open
10_chapter 5.pdf91.83 kBAdobe PDFView/Open
11_chapter 6.pdf55.57 kBAdobe PDFView/Open
12_chapter 7.pdf70.75 kBAdobe PDFView/Open
13_chapter 8.pdf11.51 kBAdobe PDFView/Open
14_references.pdf17.67 kBAdobe PDFView/Open
15_part ii_chapter 1-3.pdf73.9 kBAdobe PDFView/Open
16_chapter 4-5.pdf132.62 kBAdobe PDFView/Open
17_chapter 6-7.pdf412.66 kBAdobe PDFView/Open
18_references.pdf995.25 kBAdobe PDFView/Open


Items in Shodhganga are protected by copyright, with all rights reserved, unless otherwise indicated.