Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/324548
Title: FPGA implementation of Hybrid Processor
Researcher: Harisha M S
Guide(s): Jayadevappa D
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Jain University
Completed Date: 2020
Abstract: It is well known in worldwide, that the Processor is heart and brain of today s newlineelectronic systems that lead to development and revolution of Computers, Smart newlinephones, Wireless communications, medical electronics equipment, Aerospace, newlineDefense, and entertainment applications. Global Internet Traffic has grown from newline100GB per day in1992 to 46600GB per second in 2017. Cloud server Data handling newlinehas grown from 4 Zettabytes per year to 12 Zettabytes per year in 2019. Monthly data newlinestorage levels are at 254 Exabyte as of date. newlineTo handle the above workload of data storage, social media, data processing newlineand computation in last 30 years, the Processors have evolved with bus width of 4 bit newlineCPU to 64 bit, single core to 64 core or 192 cores (many cores), from 4000 transistors newlineto 20 billion transistors, micron wafer technology to Nano technologies, few FLOPS newlineto 15 TERA FLOPS, clock speed from MHz to GHz performance. This Processor newlineperformance improvement is unbounded and progressive, with exception of some newlinepresent day technological limitations like Memory wall, Power wall, Speed wall, newlineScaling wall etc. Hence there is a strong need to develop much more powerful and newlinecapable Processors to handle above indicated Internet traffic, data storage and newlinehandling by cloud servers and data centers. newlineAfter exhaustive data collections as a part ofthe literature survey and in depth newlinestudy of the following Processor performance parameters like Best RISC features,Best newlineCISC features,Instruction set Architectures, Multitasking, Multicore Processors, newlineMemory management, addressing modes, Timing, Power, Clock, Ports, I/O newlineInterfacing Bus, Interrupts, Interfacings,Parallelism, Pipelining, Benchmarks etc. and newlinebased on key findings a Novel and Innovative architecture leading to multi-core newlinehybrid SOC multi core (dual) hybrid Processor was proposed to take the advantage of newlinethe best features of both RISC and CISC Processor architecture. The biggest challenge newlinein such a Processor design and implementation was judicious allocation of resources newlinelike- Memory, Bus, Instructions, Speed, Power, Overall Cost, Overall Resource newlineManagement, Interfacing ability, Parallelism/Multitasking. newline newline2 newline newlineTill date, several attempts has been made to realize subset of RISC instruction newlineset and several attempts has been made by various researchers to propose some newlineminimal RISC architectures for various bit length like 8 bit, 32 bit, 64 bit using newlineVerilog and VHDL on FPGA. Many attempts have also been made till date to newlineimplement various processor related hardware interfaces (wired and wireless) on newlineFPGA, but none of them have attempted to put several and popular hardware newlineinterfaces together as a part of processor core implementation on FPGA. Hence this newlinework is very unique in itself owing to the totality of all the interfaces working together newlinesimultaneously (parallel) with other processor popular instructions using multi-core. newlineThere are several popular approaches to design and develop a contemporary newlineprocessor with several useful instructions and interfaces. The proposed approach to newlineprocessor design is Instruction and Interfacing leading to architectures. I have taken a newlinesubset of 100plus popular instructions, along with an innovatively developed newlinecommand driven instruction decoder to fetch and execute each instruction. As a part newline newlineof my experimentation with implementation of hybrid processor on FPGA. The multi- newlinecore, multi-bus and multi-level unshared Memory based novel Processor architecture newline newlinewas designed, modeling was done using Verilog, logic verification was done using newlineXilinx ISE simulator. A rapid prototype was developed using Xilinx Spartan3 FPGA newlineas a part of this research work to test all the instructions and interfaces. newlineThe key breakthrough of this research is design, development and testing of newlineSmart Core Auto Switching with smart splitter with a decision circuit to dynamically newlineallocate CPU cores and implement load balancing. With this a fully scalable, flexible, newlinerobust and open-ended architecture that can be improvised into a complex next newlinegeneration multi core Processor is developed and experimented. newline
Pagination: 130 p.
URI: http://hdl.handle.net/10603/324548
Appears in Departments:Dept. of Electronics Engineering

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certificate.pdf95.05 kBAdobe PDFView/Open
chapter-1.pdf276.3 kBAdobe PDFView/Open
chapter-2.pdf595.61 kBAdobe PDFView/Open
chapter-3.pdf552.37 kBAdobe PDFView/Open
chapter-4.pdf879.67 kBAdobe PDFView/Open
chapter-5.pdf453.3 kBAdobe PDFView/Open
chapter-6.pdf309.25 kBAdobe PDFView/Open
chapter-7.pdf441.14 kBAdobe PDFView/Open
chapter-8.pdf203.17 kBAdobe PDFView/Open
cover page.pdf10.11 kBAdobe PDFView/Open
table_of_contents.pdf87.53 kBAdobe PDFView/Open
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