Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/306421
Title: Certain Investigations on Low Power FPGA Implementation of Hybrid Method of Data Encryption
Researcher: Neelima S
Guide(s): Brindha R
Keywords: Engineering and Technology
Engineering
Engineering Electrical and Electronic
University: Avinashilingam Deemed University For Women
Completed Date: 2020
Abstract: Cryptography is the science of encrypting and decrypting of information. newlineEncryption is a process of converting readable data into unreadable format where as newlinedecryption is the process of converting the encrypted data into original form newline.Cryptography is necessary when data is communicated over any untrustworthy channel. newlineIt is implemented in many day-to-day applications such as the security of ATM card, newlinecomputer passwords in e-commerce, communication in military, etc. This thesis presents newlinethe FPGA implementation of a proposed hybrid method combining a modified SHA3 newline(Secure Hash Algorithm3) and modified AES (Advanced Encryption Standard) newlinealgorithm for encrypting data. The encryption processes are generally based on software newlinewhich requires a personal computer all the time. But portable biomedical systems need newlineminiature devices or chips for carrying out encryption .While embedded systems based newlineon microcontroller can work efficiently, the power consumption and area will be higher. newlineThe main advantage of implementing encryption algorithms in software is ease of use, newlineflexibility in upgrading whereas the drawbacks of implementing in software are poor newlinesecurity and high power consumption. The above issues motivate research in the area of newlineimplementation of encryption algorithms in hardware. The hardware is of 2 types: newlineApplication Specific Integrated Circuit (ASIC) and Field Programmable Gate Area newline(FPGA). ASIC is application dependent and is not reconfigurable whereas, FPGA is newlinereconfigurable and many applications can be implemented with ease. Thus by using newlinehardware the security, power, time and delay can be improved. The research work is newlinecarried out in different hardwares viz Cyclone III and Stratix III of 65nm technology by newlineusing the Quartus 2 tool version 9.1.
Pagination: 155 p.
URI: http://hdl.handle.net/10603/306421
Appears in Departments:Department of Electronics and Communication

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01_title.pdfAttached File96.39 kBAdobe PDFView/Open
02_certificate.pdf989.88 kBAdobe PDFView/Open
03_abstract.pdf97.65 kBAdobe PDFView/Open
04_declaration.pdf108.31 kBAdobe PDFView/Open
05_acknowledgement.pdf193.98 kBAdobe PDFView/Open
06_contents.pdf589.32 kBAdobe PDFView/Open
07_list_of_tabels.pdf196.65 kBAdobe PDFView/Open
08_list_of_figures.pdf198.67 kBAdobe PDFView/Open
09_abbrevations.pdf96.9 kBAdobe PDFView/Open
10_chapter1.pdf1.05 MBAdobe PDFView/Open
11_chapter2.pdf1.07 MBAdobe PDFView/Open
12_chapter3.pdf1.08 MBAdobe PDFView/Open
13_chapter4.pdf1.06 MBAdobe PDFView/Open
14_chapter5.pdf1.09 MBAdobe PDFView/Open
15_chpater6.pdf1.25 MBAdobe PDFView/Open
16_conclusion.pdf1.03 MBAdobe PDFView/Open
17_references.pdf1.06 MBAdobe PDFView/Open
18_annexure1.pdf160.61 kBAdobe PDFView/Open
19_annexure2.pdf2.88 MBAdobe PDFView/Open
20_publications.pdf58.49 kBAdobe PDFView/Open
80_recommendation.pdf1.13 MBAdobe PDFView/Open


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