Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/299982
Title: VLSI Design Optimization for the Development of Efficient PC RAM and MRAM Based Non Volatile Memories for FPGA Architecture
Researcher: Hamsa S
Guide(s): Ananth A.G., Thangadurai N.
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Jain University
Completed Date: 20/12/2019
Abstract: Non-volatile memories have contributed significantly in the field of computing and newlineconsumer electronics. Advancing consumer electronics demands non-volatile memories. newlineThe increasing demand of non-volatile memories has led to several emerging memory newlinetechnologies which included ferroelectric RAM, magnetic RAM, phase-change RAM. newlineAmong the functionality classification non-volatile memories are more reliable and can newlinebe programmed. Depending on the way the data is stored, the memory is classified as newlinevolatile and non-volatile. A volatile memory essentially would mean that the contents of newlinethe memory would get erased if the power goes off. Whereas non-volatile memory means newlinethat even in absence of power the memory still holds the data. The present thesis emphases newlineon designing of Non-Volatile memories like NV Static Random Access Memory (SRAM), newlineMagnetic Tunnel Junction-Magnetoresistance Random Access Memory (MTJ-MRAM) newlineand Phase Change Random Access Memory (PC-RAM). The attributes such as power newlinedissipation, delay time, area and endurance have been used for evaluating the performance newlineof the non-volatile memory circuits. newlineThe rapid progress in computing systems demands great need for emerging non-volatile newlinememories. One such computational system being Field Programmable Gate Array (FPGA) newlinewhich is mainly classified based on memory such as, SRAM based FPGA. It is required to newlinedesign a new non-volatile memory based FPGA which offers the combined advantage of newlinespeed of SRAM and non-volatility of Flash. The research work focus on design of new newlinenon-volatile memories like MTJ-MRAM and PC RAM for FPGA architecture. newlineVolatile memories like SRAM and Dynamic RAM (DRAM) are designed and behavioral newlinewaveforms are verified with attributes like power and delay for each circuit. The results newlineshowed that there is tremendous improvement in terms of power and delay in 45nm CMOS newlineTechnology design than 180nm and 90nm CMOS Technology design. The design newline newlinetransition of SRAM from volatile memory into non-volatile memory by using a non- newlinevolatile cell is performed. newline newlineThe schematics for MTJ-MRAM and PC-RAM are designed and simulations are carried newlineout in 45nm and 90nm CMOS VLSI Technology using Analog Design Environment. The newlineMTJ is modeled to behave as resistive memory using a current source. MTJ in the circuit newlineis controlled by two fields to control two layers of MTJ and modeled to behave resistive. newlinePC-RAM is modeled to behave as resistive memory using two electrodes connected to newline newlineix newline newlinechalcogenide. The output behavioral characteristics obtained show a non-volatile behavior newlinelike that of NOR-Flash memory. The attributes like power and delay are calculated and newlinecompared with SRAM and Flash memory circuits. Further this work has been extended to newlineintegrate the non-volatile memories with FPGA architecture. Existing FPGA architectures newlinewhich are non-volatile based, have limitations and demands for a better computing newlinememory to be integrated within. This work brings out a novel PC-RAM and MTJ-MRAM newlinedesign with better performance than existing SRAM based, Flash based and Anti-Fuse newlinebased types of FPGAs. The present work compares attributes of PC-RAM, MTJ-MRAM newlineand SRAM memories used for FPGA architecture. newlineThe results and analysis of the designed and implemented volatile and non-volatile newlinememory circuits clearly demonstrated that the volatile SRAM shows power dissipation newline(130 nano watts) and delay time (40 nano seconds) and DRAM shows a power dissipation newline(3 micro watts) and delay time (30 nano seconds). The design of non-volatile memory newlinecircuits such as NV SRAM shows improvement in power dissipation power dissipation newline(50.3 nano Watts) and delay time (40.58 nano seconds) compared to Volatile SRAM. The newlinenon-volatile MTJ MRAM shows good performance in power dissipation (19.97 nano newlineWatts) and delay time (15.14 femto seconds) compared to NV SRAM. The non-volatile newlinePC RAM shows better performance in power dissipation (21.04 pico Watts) compared to newlineNV SRAM and MTJ MTAM. Further PC RAM exhibits highest performance with respect newlineto power dissipation (21.04 pico Watts) and delay time (12.09 nano seconds) when newlinecompared to nor Flash memory. Further the FPGA integrated with PC RAM demonstrates newlinebetter performance in regard to power dissipation (1.15 micro Watts) and delay time (56 newlinenano seconds) compared to MTJ MRAM based FPGA that shows higher power dissipation newline(86 nano seconds) and delay (140 micro Watts) and SRAM based FPGA showing very newlinehigh power dissipation (2 milli Watts) and delay (93 micro seconds). This suggests that PC newlineRAM can be effectively used for FPGA based embedded systems and other applications newlineof future computing technology. newline
Pagination: 115 p.
URI: http://hdl.handle.net/10603/299982
Appears in Departments:Dept. of Electronics Engineering

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chapter 2.pdf287.18 kBAdobe PDFView/Open
chapter 3.pdf261.64 kBAdobe PDFView/Open
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chapter 7.pdf378.02 kBAdobe PDFView/Open
chapter 8.pdf871.64 kBAdobe PDFView/Open
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table of contents (1).pdf201.08 kBAdobe PDFView/Open


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