Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/2878
Title: Design and performance evaluation of multistage interconnection networks
Researcher: Rinkle Rani
Guide(s): Kaur, Lakhwinder
Keywords: Computer Science
Computer engineering
Computing systems
VLSI circuits
Computer networking
Upload Date: 10-Oct-2011
University: Punjabi University
Completed Date: 02/11/2010
Abstract: Most of today‟s computing systems, ranging from large parallel systems and high performance clusters to a single chip System-on-Chip (SoC), that need communication among multiple constituents, use interconnection networks. Examples of interconnection networks include the internal buses in VLSI circuits, telephone switches and networks, networks for parallel/distributed computing systems (including vector supercomputers, multi-computers, multiprocessors, cluster/network of workstations), LAN, MAN, WAN, and networks for industrial applications and electronic devices. Interconnection networks are one of the prime factors in determining the performance of such architectures, affecting the message latency, bandwidth, routing complexity, switching structure, system scalability, fault-tolerance and overall cost. A bottleneck in these parallel computing systems is the communication between processors. Therefore, the performance of interconnection networks is a critical issue in parallel computing. This has been a major driving force for the research of inter-connection networks. The study of interconnection networks in parallel computing system includes the design, performance and cost issues. Therefore, a designer is faced with several tradeoffs between performance, reliability and cost while designing interconnection networks for multiprocessor systems. The overall performance and cost-effectiveness of the existing multistage interconnection networks decreases as the network size increases, and the growth in faults has a deteriorating effect on the routing of packets from input to output nodes. Consequently, a demand for newer design interconnection networks subsists for sustained fault-tolerant operation.
Pagination: xxi, 153p.
URI: http://hdl.handle.net/10603/2878
Appears in Departments:University College of Engineering

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01_title.pdfAttached File26.54 kBAdobe PDFView/Open
02_certificate.pdf44.83 kBAdobe PDFView/Open
03_declaration.pdf27.21 kBAdobe PDFView/Open
04_acknowledgements.pdf28.12 kBAdobe PDFView/Open
05_abstract.pdf67.51 kBAdobe PDFView/Open
06_list of publications.pdf144.25 kBAdobe PDFView/Open
07_table of contents.pdf81.29 kBAdobe PDFView/Open
08_list of figures.pdf73.91 kBAdobe PDFView/Open
09_list of tables.pdf25.86 kBAdobe PDFView/Open
10_list of acronyms.pdf21.58 kBAdobe PDFView/Open
11_chapter 1.pdf195.78 kBAdobe PDFView/Open
12_chapter 2.pdf815.29 kBAdobe PDFView/Open
13_chapter 3.pdf495.35 kBAdobe PDFView/Open
14_chapter 4.pdf209.16 kBAdobe PDFView/Open
15_chapter 5.pdf259.35 kBAdobe PDFView/Open
16_chapter 6.pdf210.61 kBAdobe PDFView/Open
17_chapter 7.pdf27.98 kBAdobe PDFView/Open
18_bibliography.pdf203.25 kBAdobe PDFView/Open
19_annexure.pdf471.73 kBAdobe PDFView/Open


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