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Title: Investigations on power estimation and power delay optimization in certain digital vlsi circuits
Researcher: Ramanathan P
Guide(s): Vanathi P T
Keywords: digital vlsi circuits
information and communication engineering
power estimation
Upload Date: 21-Nov-2014
University: Anna University
Completed Date: 01/12/2009
Abstract: The advancement in Very Large Scale Integration VLSI newlinetechnology has allowed the integration of more and more functionalities onto newlinea single chip Precisely estimating power for complex digital VLSI circuits at newlinean earlier stage can save the complicated and expensive redesign task which newlinewould occur if power constraints in the specifications are violated Portable newlinesystems like notebook computers laptops mobiles and Personal Digital newlineAssistants PDA demand reduced power consumption to enhance the battery newlinelifetime There is a steady growth in the operating frequency of newlines and Digital Signal Processors DSPs in daytoday newlinelife This causes increased power dissipation which inturn can create thermal newlinehot spots This may lead to reduced circuit reliability and life expectancy newline newline
Pagination: xxviii, 184p.
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File40.76 kBAdobe PDFView/Open
02_certificate.pdf6.07 kBAdobe PDFView/Open
03_abstract.pdf17.51 kBAdobe PDFView/Open
04_acknowledgement.pdf6.59 kBAdobe PDFView/Open
05_contents.pdf60.69 kBAdobe PDFView/Open
06_chapter 1.pdf77.34 kBAdobe PDFView/Open
07_chapter 2.pdf1.44 MBAdobe PDFView/Open
08_chapter 3.pdf1.14 MBAdobe PDFView/Open
09_chapter 4.pdf1.11 MBAdobe PDFView/Open
10_chapter 5.pdf541.39 kBAdobe PDFView/Open
11_chapter 6.pdf29.04 kBAdobe PDFView/Open
12_references.pdf35.37 kBAdobe PDFView/Open
13_publications.pdf16.68 kBAdobe PDFView/Open
14_vitae.pdf6.23 kBAdobe PDFView/Open

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