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Title: A Novel Approach of AES Algorithm and it s VLSI Implementation
Researcher: C. Sapna Kumari
Guide(s): Prasad K V
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
University: Jain University
Completed Date: 15/05/2019
Abstract: The data which is being communicated can be protected in different ways. newlineFor securing sensitive data in various industries Advanced Encryption Standard (AES) is newlineused. In this topic one will understand major role in securing data. AES is a method for newlineencrypting and decrypting the data, which could be a scientific discipline rule that may be newlineused for secured data and communication in an organization. AES is also an example of newlinesymmetric key cryptographic algorithm and used in many cryptographic applications for newlineboth hardware and software. Hardware based implementation of AES algorithm is very newlineimportant and it s more secure, faster, and consumes less power as compared to its newlinesoftware-based implementation. The level of the security depends on bit size of the key, newlinemore bits in key indicates more security. AES is superior cryptography system where newlineencryption and decryption can be performed with a fixed key. AES 128 bits is a newlinesymmetric block cipher that uses the 128-bit key to encrypt and decrypt information. To newlineaddress these issues, an automated key generation, power reduction, optimization of newlinehardware resources techniques and mathematically less operation involved methods are newlineproposed and analyzed in this research work by employing different algorithms for more newlinesecurity in present communication systems. In addition to this, a hardware prototype newlinemodel on FPGA is developed and analyzed by comparing the results with existing newlineresearch work. an attempt has been made to develop a novel cryptography system for high newlinesecurity level and high speed data transfer and also encryption and decryption process. newlineThe proposed system in both software and hardware,which will reduce the hardware newlineresources in real time applications. The developed model is tested for randomly selected newlinedata and found to be the encryption and decryption process has been effective. newlinexi newlineThe prototype developed will be of low cost, high speed and its performance is also newlineagreeable with low utilization of resources like memory usage, number of flip flops, newlineslices, number of arithmetic operations etc. Also, the proposed crypto system is robust, newlineflexible, allows provision of test repeatability and re-configurability. Thus, the developed newlinemodel in software as well hardware prototype can be readily utilized in the real time newlinecommunication system to make data more secure. newline
Pagination: 107 p.
Appears in Departments:Dept. of Electronics Engineering

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certificate.pdfAttached File155.73 kBAdobe PDFView/Open
chapter 1.pdf255.36 kBAdobe PDFView/Open
chapter 2 lierature review.pdf346.13 kBAdobe PDFView/Open
chapter 3.pdf866.31 kBAdobe PDFView/Open
chapter 4.pdf1.35 MBAdobe PDFView/Open
chapter 5.pdf725.45 kBAdobe PDFView/Open
chapter 6.pdf429.93 kBAdobe PDFView/Open
chapter 7.pdf361.61 kBAdobe PDFView/Open
chapter 8.pdf128.46 kBAdobe PDFView/Open
cover page.pdf26.76 kBAdobe PDFView/Open
table of contents.pdf173.68 kBAdobe PDFView/Open
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