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Title: Efficient Algorithms for Timing Analysis and Signal Integrity for VLSI Circuits
Researcher: Singh, Sushobhit
Guide(s): Saxena, Ajay Kumar and Kalra, Prem Kumar
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
University: Dayalbagh Educational Institute
Completed Date: 2018
Abstract: Growth and advancements in electronics has played a pivotal role in the recent developments in science, technology, arts, agriculture, entertainment, etc. A dramatic event which led to widespread applications of electronics is the realization of integrated circuits, which led to miniaturization and higher effectuality of electronic devices. Electronic Design Automation (EDA) software acts as a vehicle of innovation and growth for the VLSI design industry and enables the continuum of advancements. With the increase in design density, EDA software has to adapt providing better solutions, which runs faster and consumes lesser memory. To come up with a functional design which meets all the requirements, physically realizing the design as an integrated circuit, which requires floor planning on the die area, placement of individual transistors, routing of interconnection wires, timing validation, power validation and signal integrity validation of the design elements which are synthesized from the functional design specification is a daunting task. newlineTiming analysis is central step in the design closure and is needed to be performed for design closure. In graph based analysis the problem of pessimism creates trouble in timing closure on advanced technology nodes. For this reason, designers prefer to perform a hybrid graph based and selective path based timing analysis, but even this is leading to pessimistic design closure. There is an increasing demand of all paths or exhaustive path based timing closure. In this work we have develop data structure and algorithms for exhaustive path based static timing analysis. We have also applied this data structure for partitioning the timing graph for performing distributed path based static timing analysis and proposed a couple of strategies for distribution. We have got very encouraging results for all benchmark designs that we have performed analysis, compared to DFS based strategies. We have also proved the effectiveness of our partitioning strategy on the set of benchmarks. We have also provided the memory newlineprofiles for all benchmark designs. newline newline
Appears in Departments:Department of Electrical Engineering

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01_title .pdfAttached File6.23 kBAdobe PDFView/Open
02_certificate .pdf307.82 kBAdobe PDFView/Open
03_declaration .pdf316.2 kBAdobe PDFView/Open
04_abstract .pdf143.2 kBAdobe PDFView/Open
05_acknowledgement .pdf145.32 kBAdobe PDFView/Open
06_ contents.pdf277.32 kBAdobe PDFView/Open
07_list_of_tables .pdf299.7 kBAdobe PDFView/Open
08_list_of_figures.pdf175.08 kBAdobe PDFView/Open
09_abbreviations .pdf147.84 kBAdobe PDFView/Open
10_chapter 1.pdf1.06 MBAdobe PDFView/Open
11_chapter 2 .pdf199.2 kBAdobe PDFView/Open
12_chapter 3.pdf577.11 kBAdobe PDFView/Open
13_chapter 4.pdf1.01 MBAdobe PDFView/Open
14_chapter 5.pdf1.3 MBAdobe PDFView/Open
15_conclusion .pdf1.44 MBAdobe PDFView/Open
16_references.pdf411.71 kBAdobe PDFView/Open
17_appendix.pdf347.19 kBAdobe PDFView/Open
18_summary.pdf393.31 kBAdobe PDFView/Open

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