Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/257531
Title: Development of CMOS VLSI architectures for advanced encryption standard
Researcher: Shastry, Pasumarti V Sriniwas
Guide(s): Sutaone, M S
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
Systolic
Encryption
Decryption
Isomorphic
Histograms
University: Savitribai Phule Pune University
Completed Date: 2015
Abstract: Abstract available
Pagination: xii, 141p.
URI: http://hdl.handle.net/10603/257531
Appears in Departments:College of Engineering Pune

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/01_title.pdfAttached File278.97 kBAdobe PDFView/Open
01_title.pdf278.97 kBAdobe PDFView/Open
/02_certificate.pdf456.52 kBAdobe PDFView/Open
02_certificate.pdf456.52 kBAdobe PDFView/Open
/03_declaration.pdf706.31 kBAdobe PDFView/Open
03_declaration.pdf706.31 kBAdobe PDFView/Open
/04_acknowledgement.pdf55.04 kBAdobe PDFView/Open
04_acknowledgement.pdf55.04 kBAdobe PDFView/Open
/05_abstract.pdf586.67 kBAdobe PDFView/Open
05_abstract.pdf586.67 kBAdobe PDFView/Open
/06_contents.pdf289.15 kBAdobe PDFView/Open
06_contents.pdf289.15 kBAdobe PDFView/Open
07_list of figures.pdf683.2 kBAdobe PDFView/Open
08_list of tables.pdf599.3 kBAdobe PDFView/Open
09_abbreviations.pdf188.48 kBAdobe PDFView/Open
10_chapter 1.pdf2.36 MBAdobe PDFView/Open
11_chapter 2.pdf1.93 MBAdobe PDFView/Open
12_chapter 3.pdf2.52 MBAdobe PDFView/Open
13_chapter 4.pdf8.05 MBAdobe PDFView/Open
14_chapter 5.pdf2.79 MBAdobe PDFView/Open
15_chapter 6.pdf18.29 MBAdobe PDFView/Open
16_chapter 7.pdf1.57 MBAdobe PDFView/Open
17_references.pdf1.12 MBAdobe PDFView/Open
18_publications.pdf456.87 kBAdobe PDFView/Open
19_details of indian patent filed.pdf239.11 kBAdobe PDFView/Open


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