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Title: Area and power efficient testable hardware design using high level synthesis
Researcher: Ravi S
Guide(s): Joseph M
Keywords: Engineering and Technology,Computer Science,Computer Science Hardware and Architecture
High-Level Synthesis
Power Efficient Testable Hardware
University: Anna University
Completed Date: 2018
Abstract: Nowadays, testing approaches are indispensible to test the design implemented on Programmable Logic Devices (PLDs). Field programmable Gate Arrays (FPGAs), one of the most widely used programmable devices in PLDs family, are difficult to test, due to their programmable nature, overall size, complexity, limited number of Input / Outputs (I/Os), and availability of large and variety of embedded cores on-chip. To ease the complexity of testing, several Design-For-Testability (DFT) techniques have been presented. Recently, the research community has been focusing on testing hardware at higher abstraction levels. Testability during the High-Level Synthesis (HLS) is called High Level Test Synthesis (HLTS), which has the following benefits: (i) reduced test hardware overhead, (ii) improved fault coverage, and (iii) reduced design iterations. Compared to DFT techniques applied at gate level circuits, HLTS makes the testing task easier, since it is done at higher newlineabstraction. The proposed work is a new methodology to incorporate testability with the Technology driven High-Level Synthesis (THLS), which is a customized High-level synthesis approach based on the target technology. This new methodology is called Testable Technology specific High-Level Synthesis (TTHLS), and it generates testable hardware from the corresponding HDL input. This new approach proposes Testable Technology Specific Library (TTSL), which has target technology specific test structures like scan flip-flop, Linear Feedback Shift Register (LFSR), etc. The testability incorporation at this higher abstraction, using this integrated approach, proves to be better in terms of area, and power consumption than the conventional newlineapproaches. newline newline
Pagination: xix, 128p.
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File21.95 kBAdobe PDFView/Open
02_certificates.pdf2.07 MBAdobe PDFView/Open
03_abstract.pdf5.38 kBAdobe PDFView/Open
04_acknowledgement.pdf7.81 kBAdobe PDFView/Open
05_contents.pdf15.95 kBAdobe PDFView/Open
06_list_of_abbreviations.pdf6.7 kBAdobe PDFView/Open
07_chapter1.pdf223.61 kBAdobe PDFView/Open
08_chapter2.pdf816.76 kBAdobe PDFView/Open
09_chapter3.pdf379.18 kBAdobe PDFView/Open
10_chapter4.pdf120.46 kBAdobe PDFView/Open
11_chapter5.pdf157.85 kBAdobe PDFView/Open
12_conclusion.pdf21.59 kBAdobe PDFView/Open
13_references.pdf29.5 kBAdobe PDFView/Open
14_list_of_publications.pdf9.1 kBAdobe PDFView/Open

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