Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/230428
Title: Design Of New High Performance_Low Power Full Swing Xor_Xnor Logic Gates Using Mosfet_Finfet_Cntfet Transistors
Researcher: SARADA MUSALA
Guide(s): AVIRENI SRINIVASULU
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
XOR, XNOR, PTL, TGL, Static CMOS, Pseudo logic, DCVSL, FinFET, CNTFET, Power consumption, Propagation delay, PDP, Noise analysis.
University: Vignans Foundation for Science Technology and Research
Completed Date: 2018
Abstract: The ever growing demand for portable applications like mobile phones and laptops under explosive proportions has made the designers to strive for smaller silicon area, high speed, longer battery life and more reliability. XOR/XNOR gates are the basic building blocks of various digital system applications like adders, multipliers, comparators, ALUs, MAC units, parity generators/checkers and error detection and correction coders etc. In this thesis, novel designs of different XOR/XNOR logic circuits for two input, three input, multi input, differential outputs, self checking operation, low voltage working and ternary logic are proposed. The proposed circuits used Pass transistor logic, Transmission gate logic, Static CMOS logic, Pseudo nMOS logic and DCVSL logic to design their structures. newlineAll the proposed two input, three input and multi input circuits are simple and symmetric which used the topology of pass transistor logic and transmission gate logic. All the proposed designs have good driving capability because of a full voltage rail swing at the outputs. Even though the voltage is low and frequency is high, the proposed designs produce error free outputs with the lesser transistor count. The proposed structure for multi input has less delay because of absence of cascading stage delay.The proposed circuits are area and power efficient because minimum size transistors are sufficient to build these designs that output strong levels. Also, they have less delay for the reason that their critical path consists of only a few transistors of minimum size each. The basic advantage of these circuits is their plainness in their logic and symmetry in the structure. newlineThe proposed self checking design has code disjoint, fault secure and self-testing features and display less delay and power consumption. This design has a full voltage swing at the outputs hence it has the good driving capability due to static complementary logic.
Pagination: 170
URI: http://hdl.handle.net/10603/230428
Appears in Departments:Department of Electronics and Communication Engineering

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1_title page.pdf66.03 kBAdobe PDFView/Open
2_certificate.pdf5.98 kBAdobe PDFView/Open
3_prelimenry pages.pdf70.33 kBAdobe PDFView/Open
4_chapter1.pdf240.15 kBAdobe PDFView/Open
5_chapter2.pdf215.12 kBAdobe PDFView/Open
6_chapter3.pdf405.55 kBAdobe PDFView/Open
7_chapter4.pdf276.42 kBAdobe PDFView/Open
8_chapter5.pdf1.58 MBAdobe PDFView/Open
9_chapter6.pdf21.1 kBAdobe PDFView/Open


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