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Title: Algorithm and architecture design of DDS synthesizers for improved performance of PLL
Researcher: Patel, Govind Sing
Guide(s): Sharma, Sanjay
Keywords: DDS
Electronics and communication
University: Thapar Institute of Engineering and Technology
Completed Date: 
Abstract: High speed wireless data communication is playing major role in fast development of modern communication systems. In dealing with this remarkable development, novel technologies and architectures are required to improve the performance of the system and to reduce the cost of equipment. Considering these constraints, hybrid frequency synthesis architectures and techniques have been used to overcome these constraints. The main objective of this thesis is to provide new and efficient ways to design a phase locked loop (PLL), direct digital synthesis (DDS), and hybrid PLL synthesis techniques. These techniques are generally used in various radio frequency (RF) applications, wireless communication, decoding, modulation, demodulation, etc. In the first proposed technique, the emphasis is on reducing phase noise of PLL for pure signal synthesis. For this a mathematical and modeling approach of the system has been furnished, and then output phase noises in terms of its parameters have been predicted. Based on the performance analysis, a new architecture of PLL for the reduction of phase noise is described and its operation has been verified with advanced design system (ADS) simulation tool. With the help of the proposed architecture, the phase noise has been reduced to 33.33 % at 1 Hz, 7.3 % at 100 Hz and 19 % at 100 kHz. The simulation results demonstrate the better performance as compared to the existing techniques. In digital signal processing, PLL is not capable to store and convert phase into its corresponding amplitude for the further processing. Hence, there is need to use digital technique for the synthesis in the feedback loop. This work has introduced a new direct digital frequency synthesizer (DDFS) technique using piecewise linear approximation. The proposed technique allows successive read access to memory cells per one clock cycle using time sharing. The output values will be temporarily stored and read at a later time.
Pagination: xix, 156
Appears in Departments:Department of Electronics and Communication Engineering

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