Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/228190
Title: DESIGN AND SIMULATION OF SMALL SIGNAL AND POWER MOSFETs
Researcher: Adhikari Manoj Singh
Guide(s): Singh Yashvir
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
Integrated Circuits, Multi-Finger MOSFET( MF-MOSFET), Multi-Channel MOSFET(MC-MOSFET), Reduced-Surface-Field (RESURF), Radio Frequency (RF), Short Channel Effects (SCEs), Silicon-On-Insulator (SOI).
University: Uttarakhand Technical University
Completed Date: 12-9-2017
Abstract: newlinePresently, SOI technology is dominantly used for making PICs due to its mature fabrication process with well studied native oxide. As the Si based devices are approaching their physical limits, there is need to consider the other semiconductors materials specially for high frequency devices. In the recent past, InGaAs has been recognized as promising semiconductor which can replace Si for future technology due to its excellent transport properties. Therefore, the motive of this research work is to propose the high performance MOSFET structures on Si and InGaAs for RF small signal and power applications. In the first chapter a brief introduction and various performance parameters of small signal MOSFET and power LDMOS are discussed. A brief discussion on integration of small signal and power MOSFETs is given. Historical review of small signal and power LDMOS are described in chapter second. In the third chapter design of a small signal dual channel trench MOSFET on SOI is presented. The proposed device achieves better characteristics as compared to the conventional MOSFET is discussed. In the fourth chapter a multi finger MOSFET on SOI is presented. A high performance InGaAs dual channel MOSFET and its various performance parameters is presented in the fifth chapter. In the sixth chapter a multi channel MOSFET on InGaAs material is proposed. A new DCTG LDMOS structure on InGaAs material by incorporating trenches in the planar technology is presented in the seventh chapter. Two dimensional simulations are performed to optimize the DCTG LDMOS structure and compare the performance parameters with the conventional LDMOS for identical cell pitch and gate length. In the eighth chapter the integration of small signal MOSFET and power LDMOS on InGaAs is presented. In the last chapter conclusions drawn from the simulations and theoretical investigations are discussed. newline newline newline newline
Pagination: 156 pages
URI: http://hdl.handle.net/10603/228190
Appears in Departments:Department of Electronics and Communication Engineering

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01-title page.pdfAttached File126.01 kBAdobe PDFView/Open
02-certificate.pdf1.08 MBAdobe PDFView/Open
03-acknowledgements.pdf47.79 kBAdobe PDFView/Open
04-contents.pdf71.93 kBAdobe PDFView/Open
05-list-of-figures.pdf62.89 kBAdobe PDFView/Open
06-list-of-tables.pdf40.92 kBAdobe PDFView/Open
07-list of abbreviations.pdf59.58 kBAdobe PDFView/Open
08-chapter 1.pdf220.6 kBAdobe PDFView/Open
09-chapter 2.pdf190.2 kBAdobe PDFView/Open
10-chapter 3.pdf286.27 kBAdobe PDFView/Open
11-chapter 4.pdf307.23 kBAdobe PDFView/Open
12-chapter 5.pdf276.12 kBAdobe PDFView/Open
13-chapter 6.pdf296.34 kBAdobe PDFView/Open
14-chapter 7.pdf344.12 kBAdobe PDFView/Open
15-chapter 8.pdf275.39 kBAdobe PDFView/Open
16-chapter 9.pdf67.31 kBAdobe PDFView/Open
17-references.pdf136.82 kBAdobe PDFView/Open
18-publications.pdf88.95 kBAdobe PDFView/Open


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