Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/224866
Title: Analysis and Design of High Speed Low Offset Power Efficient Dynamic CMOS Comparator in 180nm Technology
Researcher: Gandhi Priyesh
Guide(s): Devashrayee N M
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
University: Nirma University
Completed Date: 30/08/2018
Abstract: The Analog to Digital converters (ADCs) and Digital-to-Analog converters (DACs) are the newlinekey interface blocks between the continuous time domain and the discrete-time digital newlinedomain. They are found in an extensive range of devices in consumer electronics, medical newlineequipment, communication and instrumentation applications, and current growing areas newlineand#1048648;and#1048593;and#1048650;and#1048593;and#1048579;and#1048620;and#1048657;and#1048663;and#1048648;and#1048661;and#1048657;and#1048648;and#1048663;and#1048579;and#1048658;and#1048649;and#1048579;and#1048631;and#1048651;and#1048652;and#1048657;and#1048650;and#1048662;and#1048579;and#1048587;and#1048620;and#1048658;and#1048631;and#1048588;and#1048591;and#1048579;and#1048644;and#1048655;and#1048655;and#1048579;and#1048659;and#1048658;and#1048661;and#1048663;and#1048644;and#1048645;and#1048655;and#1048648;and#1048579;and#1048662;and#1048668;and#1048662;and#1048663;and#1048648;and#1048656;and#1048662;and#1048579;and#1048652;and#1048657;and#1048579;and#1048663;and#1048658;and#1048647;and#1048644;and#1048668;and#1048758;and#1048662;and#1048579;and#1048655;and#1048652;fe, and wearable devices etc. newlineThe basic building blocks of a ADCs and DACs consist of analog circuits such as voltage newlinereference, operational amplifiers as well as mixed signal circuits such as comparators. newlineBesides data converters, the comparator has many other applications such as memory, newlinerelaxation oscillators, null detector, zero-crossing detectors, peak detectors, switching newlinepower regulators, high-speed wireless and wireline communication systems, and many newlinemore. This has generated a enormous demand for high-speed low offset power efficient newlinecomparator that can be realized in a mainstream submicron CMOS technology. newlineThe ever increasing need of high speed, area efficient, high precision and power efficient newlineanalog-to-digital converter forces towards the exploration and usage of the dynamic newlinecomparator to optimize power, area and maximize the speed. In this research, a new newlineflanged high-speed low offset power efficient voltage comparator architecture is newlineintroduced. newlineThe analysis and design of a high speed low offset power efficient dynamic CMOS newlinecomparator based on fully differential and double tail structure is presented. A novel newlineconcept of fully differential double tail dynamic comparator (FDDTDC) realized with newlinehigh-speed, low offset with optimized power and area than that of the conventional newlinedynamic comparators is proposed. The simulation is carried out using 180 nm CMOS newlinetechnology with a supply voltage of ±0.9 V, at 1.3 GHz of frequency resulting into the newlinedelay of 0.37 ns while consuming 265.25 and#1049117;W of power. The proposed comparator has
Pagination: 
URI: http://hdl.handle.net/10603/224866
Appears in Departments:Institute of Technology

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10_nomenclature.pdfAttached File38.12 kBAdobe PDFView/Open
11_chapter1.pdf181.26 kBAdobe PDFView/Open
12_chapter2.pdf647.09 kBAdobe PDFView/Open
13_chapter3.pdf1.1 MBAdobe PDFView/Open
14_chapter4.pdf4.37 MBAdobe PDFView/Open
15_chapter5.pdf6.61 MBAdobe PDFView/Open
16_chapter6.pdf30.9 kBAdobe PDFView/Open
17_references.pdf91.25 kBAdobe PDFView/Open
18_appendix.pdf1.43 MBAdobe PDFView/Open
19_list of publication.pdf10.26 kBAdobe PDFView/Open
1_title.pdf110.58 kBAdobe PDFView/Open
2_certificate.pdf229.37 kBAdobe PDFView/Open
6_contents.pdf28.38 kBAdobe PDFView/Open
7_list_of_figures.pdf41.11 kBAdobe PDFView/Open
8_list_of_tables.pdf16.61 kBAdobe PDFView/Open
9_abbreviation.pdf20.26 kBAdobe PDFView/Open


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