Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/220332
Title: quotTowards Realizing Low Quantum Cost Reversible Logic Circuitsquot
Researcher: Sai, Phaneendra
Guide(s): M. B. Srinivas
Keywords: Engineering and Technology, EEE, Low Quantum, Logic Circuits
University: Birla Institute of Technology and Science
Completed Date: 2017
Abstract: Research on reversible logic gained momentum in the past decade owing to its applications newlinein quantum computing and low power circuit implementation. Reversible circuits newlinerealized by the existing synthesis techniques are often sub-optimal and optimization newlinetechniques are applied on them to reduce the cost , a metric used to compare reversible newlinecircuits. While several optimization techniques are present in the literature, finding optimal or near-optimal reversible circuit is still an open-problem. In this thesis, a set of optimization techniques is proposed that can be applied on a pair of gates to reduce the cost of a reversible circuit. Initially, a decomposition newlinetechnique is presented that decomposes a pair of gates into a set of smaller gates newlinewithout changing the functionality. This technique is then used in conjunction with newlinean Exclusive-OR Sum-of-Product (ESOP) based reversible circuit synthesis algorithm newlineto check its efficiency. It is known that the decomposition technique does not always newlineresult in cost reduction for a given gate pair. This leads us to examine the condition newlinethat results in reduction and it has been found that the effectiveness of this technique is proportionate to the number of common control lines between the gate pair. In order to increase the number of common control lines, a transformation approach is presented. Lastly, a representation is proposed to classify a pair of gates according to their control line characteristics. This classification helps in identifying the gate pairs that can be optimized as opposed to those that can not be. Based on this classification, a newlinemethodology is presented to reduce the cost of a given gate pair. In order to apply the newlineproposed techniques on reversible circuits, these techniques are integrated into greedy newlineoptimization algorithms. A set of benchmark circuits is applied on these algorithms newlineand are compared with existing benchmark circuits. Results indicate that the proposed newlinetechniques lead to significant improvement in the cost of reversible circuit.
Pagination: 111p.
URI: http://hdl.handle.net/10603/220332
Appears in Departments:Electrical & Electronics Engineering

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