Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/208513
Title: Modeling Deep Submicron MOS Transistor for Ultra Low Power Analog and RF circuit Design
Researcher: Singh, Kirmender
Guide(s): Jain, R. C. and Bhattacharyya, A. B.
Keywords: electronics
Internet of Things
MOS transistor
nanoscale CMOS
VLSI community
University: Jaypee Institute of Information Technology
Completed Date: 07/06/2018
Abstract: included newline
URI: http://hdl.handle.net/10603/208513
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File43.41 kBAdobe PDFView/Open
02_table of contents.pdf51.4 kBAdobe PDFView/Open
03_declaration.pdf7.22 kBAdobe PDFView/Open
04_certificate.pdf7.19 kBAdobe PDFView/Open
05_acknowledgements.pdf11.96 kBAdobe PDFView/Open
06_abstract.pdf43.44 kBAdobe PDFView/Open
07_list of figures & tables.pdf71.76 kBAdobe PDFView/Open
08_list of acronyms and abbreviations & symbols.pdf46.67 kBAdobe PDFView/Open
09_chapter1.pdf114.77 kBAdobe PDFView/Open
10_chapter2.pdf103.52 kBAdobe PDFView/Open
11_chapter3.pdf311.09 kBAdobe PDFView/Open
12_chapter4.pdf150.76 kBAdobe PDFView/Open
13_chapter5.pdf229.86 kBAdobe PDFView/Open
14_chapter6.pdf407.79 kBAdobe PDFView/Open
15_chapter7.pdf495.25 kBAdobe PDFView/Open
16_chapter8.pdf400.7 kBAdobe PDFView/Open
17_chapter9.pdf59.97 kBAdobe PDFView/Open
18_appendix.pdf264.27 kBAdobe PDFView/Open
19_references.pdf58.33 kBAdobe PDFView/Open
20_list of publications.pdf24.55 kBAdobe PDFView/Open
21_synopsis.pdf166.86 kBAdobe PDFView/Open


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