Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/195725
Title: Power minimization in arithmetic logic unit design using clock gating techniques for high speed circuits
Researcher: L, Raja
Guide(s): Thanushkodi, K
Keywords: Arithmetic
Gating
Latches
Methodology
Optimization
University: Anna University
Completed Date: 2016
Abstract: Abstract available
Pagination: xviii, 133p.
URI: http://hdl.handle.net/10603/195725
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File116.98 kBAdobe PDFView/Open
02_certificate.pdf972.89 kBAdobe PDFView/Open
03_abstract.pdf266.09 kBAdobe PDFView/Open
04_acknowledgement.pdf81.65 kBAdobe PDFView/Open
05_table of content.pdf469.04 kBAdobe PDFView/Open
06_list of table.pdf104.03 kBAdobe PDFView/Open
07_list of figures.pdf346.59 kBAdobe PDFView/Open
08_list of symbols and abbreviations.pdf210.13 kBAdobe PDFView/Open
09_chapter 1.pdf6.46 MBAdobe PDFView/Open
10_chapter 2.pdf1.81 MBAdobe PDFView/Open
11_chapter 3.pdf8.26 MBAdobe PDFView/Open
12_chapter 4.pdf5.34 MBAdobe PDFView/Open
13_chapter 5.pdf3.37 MBAdobe PDFView/Open
14_chapter 6.pdf403.58 kBAdobe PDFView/Open
15_references.pdf2.19 MBAdobe PDFView/Open
16_list of publication.pdf288.15 kBAdobe PDFView/Open


Items in Shodhganga are protected by copyright, with all rights reserved, unless otherwise indicated.

Altmetric Badge: