Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/18196
Title: Low poer and area efficient 128 point pipelined fft processor using mixed radix 42 for ofdm applications
Researcher: K. Umapathy
Guide(s): Dr. D. Rajaveerappa
Keywords: Electronics and Communication Engineering
Low power and area efficient 128 point pipelined FFT processor
Using mixed radix 4/2 for OFDM applications
Upload Date: 7-May-2014
University: Jawaharlal Nehru Technological University, Anantapuram
Completed Date: 01/08/2013
Abstract: The Discrete Fourier Transform (DFT) is an important technique in the field of Digital Signal Processing (DSP) and Telecommunications, especially for applications in Orthogonal Frequency Division Multiplexing (OFDM) systems. The Fast Fourier Transform (FFT) is an efficient algorithm to compute the DFT and its inverse. The FFT processor plays a key role in the field of communication systems such as Digital Video or Audio Broadcasting, Wireless LAN with Standards of IEEE 802.11, High Speed Digital Subscriber Lines etc. Since FFT processor is a complex module in OFDM, it is highly inevitable to design the processor in an efficient way. This research work involves the implementation of a low power and area efficient 128-point pipelined FFT processor using Mixed Radix 4/2 for OFDM applications. The design and implementation of the FFT processor has been achieved using Cached-memory architecture (CMA) and the Mixed Radix 4/2 Multiple Delay Commutator algorithm (R42MDC) to reduce the size and power. From the Literature Survey, it is understood that large number of research papers have focused on the implementation of efficient pipelined FFT processors to understand the impact of power, area and hardware complexity against the performance of the processors for OFDM applications. Moreover, there are no much literature available relating to the implementation of 128 point pipelined FFT processors for OFDM applications. Hence the present investigation is carried out. newlineInitially in this work, the implementation of a 128 point FFT processor has been achieved using Single Delay Feedback (SDF) architecture with the algorithms of Radix 2 FFT and Mixed Radix 4/2 FFT individually and their power or area statistics are computed. Then a low power and area efficient 128-point FFT processor for newlinev newlineOFDM systems is implemented using Cached-memory architecture (CMA) and Mixed Radix 4-2 Multiple Delay Commutator (R42MDC) algorithm to process the real time high speed data. The various types of pipeline architectures such as Multiple Delay Co
Pagination: x,104 p
URI: http://hdl.handle.net/10603/18196
Appears in Departments:Department of Electronics and Communication

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01_title.pdfAttached File33.52 kBAdobe PDFView/Open
02_certificates.pdf9.72 kBAdobe PDFView/Open
03_acknowledgements.pdf8.93 kBAdobe PDFView/Open
04_preface.pdf8.45 kBAdobe PDFView/Open
05_contents.pdf8.14 kBAdobe PDFView/Open
06_list of tables figures.pdf15.15 kBAdobe PDFView/Open
07_chapter 1.pdf249.24 kBAdobe PDFView/Open
08_chapter 2.pdf74.16 kBAdobe PDFView/Open
09_chapter 3.pdf56.81 kBAdobe PDFView/Open
10_chapter 4.pdf466.72 kBAdobe PDFView/Open
11_chapter 5.pdf474.53 kBAdobe PDFView/Open
12_chapter 6.pdf683.43 kBAdobe PDFView/Open
13_chapter 7.pdf178.49 kBAdobe PDFView/Open
14_chapter 8.pdf38.21 kBAdobe PDFView/Open
15_references.pdf23.08 kBAdobe PDFView/Open


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