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Title: Analysis and diagnosis of stuck at and bridging faults in reed muller canonical exclusive or sum of product circuits
Researcher: Geetha V
Guide(s): Devarajan N
Keywords: Electrical engineering
Exclusive-OR Sum of Products
Reed-Muller Canonical
Upload Date: 24-Feb-2014
University: Anna University
Completed Date: 01/11/2013
Abstract: Testability aspects have been included in modern designs as an newlineessential component of the design specifications. Consideration in the early newlinedesigns were technology and mathematical tractability oriented only in newlinespecifying devices and structure. Modern approaches or solutions will have newlineto additionally consider the testability of the devices and/or the network newlinestructure, since the test set i.e. the set of test input patterns depend on the newlinenetwork topology and the devices used. With recent improvements in layout newlinetechnology and increased use of field programmable gate arrays, where the newlineXOR gate is manufactured as a basic cell component, logic circuits based on newlineAND-XOR realizations have gained interest. The AND-XOR realizations are newlinevery efficient for large classes of circuits. In several applications, the ANDXOR newlinerealizations may occupy less chip area than that of the traditional ANDOR newlinesynthesis. The XOR-based circuits have good testability properties and newlineare thus well-suited for the design for testability. The literature survey shows that research is being carried out for newlineabout four decades in the field of fault detection in digital circuits, especially newlinewith the network structure of Reed-Muller Canonical (RMC) forms. Test newlinevectors for determining various types of faults such as the basic single stuckat, newlinemultiple stuck-at and bridging faults had been tried out with modifications newlineof the basic Exclusive-OR Sum of Products (ESOP) networks. The cardinality newlineof the test vectors proposed by many authors become prohibitively excessive newlinefor large number of input variables. newline
Pagination: xxii, 182p.
Appears in Departments:Faculty of Electrical and Electronics Engineering

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02_certificate.pdf265.52 kBAdobe PDFView/Open
03_abstract.pdf24.18 kBAdobe PDFView/Open
04_acknowledgements.pdf339.31 kBAdobe PDFView/Open
05_contents.pdf65.87 kBAdobe PDFView/Open
06_chapter1.pdf167.73 kBAdobe PDFView/Open
07_chapter2.pdf144.66 kBAdobe PDFView/Open
08_chapter3.pdf97.05 kBAdobe PDFView/Open
09_chapter4.pdf245.37 kBAdobe PDFView/Open
10_chapter5.pdf112.23 kBAdobe PDFView/Open
11_chapter6.pdf105.88 kBAdobe PDFView/Open
12_chapter7.pdf108.03 kBAdobe PDFView/Open
13_chapter8.pdf112.83 kBAdobe PDFView/Open
14_chapter9.pdf105.42 kBAdobe PDFView/Open
15_chapter10.pdf159.45 kBAdobe PDFView/Open
16_chapter11.pdf28.14 kBAdobe PDFView/Open
17_references.pdf62.2 kBAdobe PDFView/Open
18_publications.pdf22.47 kBAdobe PDFView/Open
19_vitae.pdf19.34 kBAdobe PDFView/Open

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